JAJSS49A December   2023  – June 2024 TPS62916E

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Smart Config (S-CONF)
      2. 6.3.2  Device Enable (EN/SYNC)
      3. 6.3.3  Device Synchronization (EN/SYNC)
      4. 6.3.4  Spread Spectrum Modulation
      5. 6.3.5  Output Discharge
      6. 6.3.6  Undervoltage Lockout (UVLO)
      7. 6.3.7  Power-Good Output
      8. 6.3.8  Noise Reduction and Soft-Start Capacitor (NR/SS)
      9. 6.3.9  Current Limit and Short-Circuit Protection
      10. 6.3.10 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Fixed Frequency Pulse Width Modulation
      2. 6.4.2 Low Duty Cycle Operation
      3. 6.4.3 High Duty Cycle Operation (100% Duty Cycle)
      4. 6.4.4 Second Stage L-C Filter Compensation (Optional)
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Custom Design With WEBENCH® Tools
        2. 7.2.2.2 External Component Selection
          1. 7.2.2.2.1 Switching Frequency Selection
          2. 7.2.2.2.2 Inductor Selection for the First L-C Filter
          3. 7.2.2.2.3 Output Capacitor Selection
          4. 7.2.2.2.4 Ferrite Bead Selection for Second L-C Filter
          5. 7.2.2.2.5 Input Capacitor Selection
          6. 7.2.2.2.6 Setting the Output Voltage
          7. 7.2.2.2.7 NR/SS Capacitor Selection
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 サード・パーティ製品に関する免責事項
      2. 8.1.2 Development Support
        1. 8.1.2.1 Custom Design With WEBENCH® Tools
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 ドキュメントの更新通知を受け取る方法
    4. 8.4 サポート・リソース
    5. 8.5 Trademarks
    6. 8.6 静電気放電に関する注意事項
    7. 8.7 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.5 Electrical Characteristics

Over recommended input voltage range, TJ= –55℃ to 150℃. Typical values are at Vin = 12 V and TJ = 25℃ (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY
IQ Quiescent current EN = High, no load, device switching, fsw = 1 MHz 5 mA
ISD Shutdown current EN = GND, TJ = –55°C to 150°C 0.3 70 µA
VUVLO Undervoltage lockout VIN rising, TJ = –40°C to 125°C 2.85 2.92 3.0 V
VHYS Undervoltage lockout hysteresis 200 mV
TJSD Thermal shutdown threshold TJ rising 170 °C
Thermal shutdown hysteresis TJ falling 20 °C
CONTROL and INTERFACE
VH_EN High-level input-threshold voltage at EN/SYNC 0.97 1.01 1.04 V
VL_EN Low-level input-threshold voltage at EN/SYNC 0.87 0.9 0.93 V
VH_SYNC High-level input-threshold clock signal on EN/SYNC EN/SYNC = clock 1.1 V
VL_SYNC Low-level input-threshold clock signal on EN/SYNC EN/SYNC = clock 0.4 V
IEN,LKG Input leakage current into EN/SYNC EN/SYNC = GND or VIN, –40 ℃ ≤ TJ ≤ 125 ℃ 5 160 nA
RPD Pulldown resistor on EN/SYNC EN/SYNC = Low 330 500 kΩ
tdelay Enable delay time Time from EN/SYNC high to device starts switching, RS-CONF = 80.6 kΩ 1 ms
INR/SS NR/SS source current 67.5 75 82.5 µA
RS-CONF S-CONF resistor step range accuracy RS-CONF tolerance for all settings according to S-CONF Table –4 +4 %
VPG Power-good threshold VFB rising, referenced to VFB nominal 93 95 98 %
VPG Power-good threshold VFB falling, referenced to VFB nominal 88 90 93 %
VPG,OL Low-level output voltage at PG pin ISINK = 1 mA 0.4 V
IPG,LKG Input leakage current into PG pin VPG = 5 V; –40℃ ≤ TJ ≤ 125℃ 5 500 nA
tPG,DLY Power-good delay time VFB falling 9 µs
OUTPUT
ton Minimum on-time VIN ≥ 5 V, Iout = 1 A 35 ns
toff Minimum off-time VIN ≥ 5 V, Iout = 1 A 50 ns
VFB Feedback regulation accuracy –55℃ ≤ TJ  ≤ 150℃ 0.792 0.8 0.808 V
IFB,LKG Input leakage current into FB VFB = 0.8 V, –40℃ ≤ TJ ≤ 125℃ 1 70 nA
IVO,LKG Input leakage current into VO VVO = 1.2 V, –40℃ ≤ TJ ≤ 125℃ 0.01 30 µA
PSRR Power supply rejection ratio VIN = 12 V, 1.2 VOUT, 1 A, CNR/SS = 470 nF, fsw = 1 MHz, CFF = open, L1 = 1 µH, COUT = 4 × 22 µF, f ≤ 100  kHz 65 dB
PSRR Power supply rejection ratio VIN = 5 V, 1.2 VOUT, 1 A, CNR/SS = 470 nF, fsw = 2.2 MHz, CFF = open, L1 = 1µH, COUT = 4 x 22 µF, f ≤ 100  kHz 70 dB
VNRMS Output voltage RMS noise VIN = 12 V, BW = 100 Hz to 100 kHz, CNR/SS = 470 nF, fSW = 1 MHz, VOUT = 1.2 V, CFF = open, L1 = 1 µH, COUT = 4 × 22 µF 24.4 µVRMS
VNRMS Output voltage RMS noise VIN = 5 V, BW = 100 Hz to 100 kHz, CNR/SS = 470 nF, fSW = 2.2 MHz, VOUT = 1.2 V, CFF = open, L1 = 1 µH, COUT = 4 × 22 µF 16.5 µVRMS
Vopp Output ripple voltage at fSW VIN = 12 V, fSW = 1 MHz, VOUT = 1.2 V, L1 = 1 µH, COUT = 4 × 22 µF, Lf = 10 nH, Cf = 22 µF 36 µVRMS
Vopp Output ripple voltage at fSW VIN = 5 V, fSW = 2.2 MHz, VOUT = 1.2 V, L1 = 2.2 µH, 4OUT = 3 × 22 µF, Lf = 10 nH, Cf = 22 uF 13 µVRMS
RDIS Output discharge resistance EN/SYNC = GND, VOUT = 1.2V, VIN ≥ 5 V. 4 Ω
RDIS Output discharge resistance EN/SYNC = GND, VOUT = 5 V, VIN ≥ 5 V. 16 Ω
fSW Switching frequency 2.2 MHz setting 1.98 2.2 2.42 MHz
fSW Switching frequency 1.4 MHz setting 1.26 1.4 1.54 MHz
fSW Switching frequency 1 MHz setting 0.9 1 1.18 MHz
DSYNC Synchronization duty cycle 45 55 %
tsync_elay Synchronization phase delay Phase delay from EN/SYNC rising edge to SW rising edge 90 ns
ISWpeak Peak switch current limit 8.6 9 9.6 A
ISWvalley Valley switch current limit 8.8 A
Inegvalley Negative valley current limit –2.9 –2 A
RDS(ON) High-side FET on-resistance VIN ≥ 5V 25 mΩ
Low-side FET on-resistance VIN ≥ 5V 7 mΩ