JAJSLL1C November   2023  – June 2024 TPS62914 , TPS62916 , TPS62918

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Smart Config (S-CONF)
      2. 6.3.2  Device Enable (EN/SYNC)
      3. 6.3.3  Device Synchronization (EN/SYNC)
      4. 6.3.4  Spread Spectrum Modulation
      5. 6.3.5  Output Discharge
      6. 6.3.6  Undervoltage Lockout (UVLO)
      7. 6.3.7  Power-Good Output
      8. 6.3.8  Noise Reduction and Soft-Start Capacitor (NR/SS)
      9. 6.3.9  Current Limit and Short-Circuit Protection
      10. 6.3.10 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Fixed Frequency Pulse Width Modulation
      2. 6.4.2 Low Duty Cycle Operation
      3. 6.4.3 High Duty Cycle Operation (100% Duty Cycle)
      4. 6.4.4 Second Stage L-C Filter Compensation (Optional)
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Custom Design With WEBENCH® Tools
        2. 7.2.2.2 External Component Selection
          1. 7.2.2.2.1 Switching Frequency Selection
          2. 7.2.2.2.2 Inductor Selection for the First L-C Filter
          3. 7.2.2.2.3 Output Capacitor Selection
          4. 7.2.2.2.4 Ferrite Bead Selection for Second L-C Filter
          5. 7.2.2.2.5 Input Capacitor Selection
          6. 7.2.2.2.6 Setting the Output Voltage
          7. 7.2.2.2.7 Bootstrap Capacitor Selection
          8. 7.2.2.2.8 NR/SS Capacitor Selection
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 サード・パーティ製品に関する免責事項
      2. 8.1.2 Development Support
        1. 8.1.2.1 Custom Design With WEBENCH® Tools
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 ドキュメントの更新通知を受け取る方法
    4. 8.4 サポート・リソース
    5. 8.5 Trademarks
    6. 8.6 静電気放電に関する注意事項
    7. 8.7 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.2.1 Design Requirements

The external components have to fulfill the needs of the application, but also meet the stability criteria of the control loop of the device. The device is designed to work within a range of external components, and can be optimized for efficiency, output ripple, component count, or lowest 1/f noise.

Typical applications that have input voltages of ≤ 6 V use a 1 µH inductor with a 2.2 MHz switching frequency. Applications that have input voltages > 6 V can be optimized for efficiency using a 1 µH inductor with a 1 MHz or 1.4 MHz switching frequency depending on the output voltage. Optimization for powering clock and PLL circuits that need a 3.3 V output use a 1 µH inductor with 2.2 MHz switching frequency, minimizing output voltage ripple and low frequency noise.

For the application cases that are not found in Table 7-2, there are two methods to design the TPS6291x circuit. Section 7.2.2.1 uses WEBENCH to design the circuit automatically or the calculations in Section 7.2.2.2 can be used instead.

Table 7-2 Typical Single L-C Filter Design Recommendations
DESIGN GOAL VIN VOUT FSW INDUCTOR (2) OUTPUT CAPACITORS (3)
Typical 12 V(1) ≤ 1.4 V(1) 1 MHz 1 µH 6 × 22 µF, 10 V, 0805
Typical 12 V 1.4 V < VOUT ≤ 2.2 V 1.4 MHz 1 µH 6 × 22 µF, 10 V, 0805
Typical 12 V > 2.2 V 2.2 MHz 1 µH 8 × 22 µF, 10 V, 0805
Typical 5 V ≤ 3.3 V 2.2 MHz 1 µH 6 × 22 µF, 10 V, 0805
Typical 5 V > 3.3V 2.2 MHz 1 µH 8 × 22 µF, 10 V, 0805
(1) The maximum input to output voltage difference is limited by the device maximum minimum on-time of 70 ns. This limit is especially important for input voltages above 12 V or output voltages below 1 V. See Section 7.2.2.2.1.
(2) For inductor part numbers, see Table 7-4.
(3) For output capacitor part numbers, see Table 7-6.

The second stage L-C filter is optional, as the device can be used without this filter to achieve below 20 μVRMS noise typically. A second stage filter is added to provide additional attenuation of the output ripple voltage. The output voltage is sensed after the second L-C filter by connecting the FB resistors to the second stage L-C filter capacitor. This action provides remote sense, minimizing output voltage drop due to the ferrite bead. Refer to Table 7-3 for second stage L-C filter recommendations based on the output voltage.

Table 7-3 Second Stage L-C (Ferrite Bead) Filter Design Recommendations
VOUT (V) FERRITE BEAD IMPEDANCE (AT 100 MHZ)(2) OUTPUT CAPACITORS (1)
≤ 2.2 V 8 to 20 Ω 1 × 22 µF, 10 V, 0805
> 2.2 V 8 to 20 Ω 2 × 22 µF, 10 V, 0805
(1) For output capacitor part numbers, see Table 7-6.
(2) For second stage L-C filter part numbers, see Table 7-6.