JAJSM42C may   2021  – march 2023 TPS629210-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Thermal Information - DYC Package
    6. 7.6 Electrical Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Mode Selection and Device Configuration (MODE/S-CONF Pin)
      2. 8.3.2 Adjustable VO Operation (External Voltage Divider)
      3. 8.3.3 Selectable VO Operation (VSET and Internal Voltage Divider)
      4. 8.3.4 Smart Enable with Precise Threshold
      5. 8.3.5 Power Good (PG)
      6. 8.3.6 Output Discharge Function
      7. 8.3.7 Undervoltage Lockout (UVLO)
      8. 8.3.8 Current Limit and Short Circuit Protection
      9. 8.3.9 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Forced Pulse Width Modulation (PWM) Operation
      2. 8.4.2 Power Save Mode Operation (Auto PFM/PWM)
      3. 8.4.3 AEE (Automatic Efficiency Enhancement)
      4. 8.4.4 100% Duty-Cycle Operation
      5. 8.4.5 Starting into a Prebiased Load
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Custom Design With WEBENCH® Tools
        2. 9.2.2.2 Programming the Output Voltage
        3. 9.2.2.3 External Component Selection
          1. 9.2.2.3.1 Output Filter and Loop Stability
          2. 9.2.2.3.2 Inductor Selection
          3. 9.2.2.3.3 Capacitor Selection
            1. 9.2.2.3.3.1 Output Capacitor
            2. 9.2.2.3.3.2 Input Capacitor
      3. 9.2.3 Application Curves
    3. 9.3 System Examples
      1. 9.3.1 Powering Multiple Loads
      2. 9.3.2 Inverting Buck-Boost (IBB)
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
      3. 9.5.3 Thermal Considerations
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 サード・パーティ製品に関する免責事項
      2. 10.1.2 Development Support
        1. 10.1.2.1 Custom Design With WEBENCH® Tools
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 ドキュメントの更新通知を受け取る方法
    4. 10.4 サポート・リソース
    5. 10.5 Trademarks
    6. 10.6 静電気放電に関する注意事項
    7. 10.7 用語集
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3.3 Selectable VO Operation (VSET and Internal Voltage Divider)

If the device is configured to VSET operation, the device interprets the VSET pin value following the MODE/S-CONF readout (see Figure 8-3). There is no further interpretation of the VSET pin during operation and the output voltage cannot be changed afterward without toggling the EN pin.

Figure 8-3 shows the typical schematic for this configuration, where VO is directly sensed at the VOS pin of the device. VO is sensed only through the VOS pin by an internal resistor divider. The target VO is programmed by an external resistor connected between VSET and GND (see Table 8-2).

GUID-20210614-CA0I-QTHN-57JK-RBPCRCJ8Q778-low.svg Figure 8-3 Selectable VO Operation Schematic
Table 8-2 VSET Selection Table
VSET # Resistor Value [Ω](1) Target VO [V]
1 GND 1.2
2 4.87 k 0.4
3 6.04 k 0.6
4 7.50 k 0.8
5 9.31 k 0.85
6 11.50 k 1.0
7 14.30 k 1.1
8 17.80 k 1.25
9 22.10 k 1.3
10 27.40 k 1.35
11 34.00 k 1.8
12 42.20 k 1.9
13 52.30 k 2.5
14 64.90 k 3.8
15 80.60 k 5.0
16 100.00 k 5.1
17 124.00 k 5.5
18 249.00 k or larger/open 3.3
(1) E96 Resistor Series, 1% accuracy, temperature coefficient better or equal to ±200 ppm/°C