JAJSM61B August   2021  – January 2022 TPS629210

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Mode Selection and Device Configuration (MODE/S-CONF Pin)
      2. 8.3.2 Adjustable VO Operation (External Voltage Divider)
      3. 8.3.3 Selectable VO Operation (VSET and Internal Voltage Divider)
      4. 8.3.4 Smart Enable with Precise Threshold
      5. 8.3.5 Power Good (PG)
      6. 8.3.6 Output Discharge Function
      7. 8.3.7 Undervoltage Lockout (UVLO)
      8. 8.3.8 Current Limit and Short Circuit Protection
      9. 8.3.9 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Forced Pulse Width Modulation (PWM) Operation
      2. 8.4.2 Power Save Mode Operation (Auto PFM/PWM)
      3. 8.4.3 AEE (Automatic Efficiency Enhancement)
      4. 8.4.4 100% Duty-Cycle Operation
      5. 8.4.5 Starting into a Pre-Biased Load
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Custom Design With WEBENCH® Tools
        2. 9.2.2.2 Programming the Output Voltage
        3. 9.2.2.3 External Component Selection
          1. 9.2.2.3.1 Output Filter and Loop Stability
          2. 9.2.2.3.2 Inductor Selection
          3. 9.2.2.3.3 Capacitor Selection
            1. 9.2.2.3.3.1 Output Capacitor
            2. 9.2.2.3.3.2 Input Capacitor
      3. 9.2.3 Application Curves
    3. 9.3 System Examples
      1. 9.3.1 Powering Multiple Loads
      2. 9.3.2 Inverting Buck-Boost (IBB)
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
      1. 11.2.1 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
      2. 12.1.2 Development Support
        1. 12.1.2.1 Custom Design With WEBENCH® Tools
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 サポート・リソース
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics

VI = 3 V to 17 V, TJ = –40°C to +125°C, Typical values at VI = 12 V and TA = 25 °C, unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY
IQ Operating quiescent current (power save mode) IOUT = 0 mA,  device not switching 4 µA
IQ;PWM Operating quiescent current (PWM mode) VIN = 12 V, VOUT = 1.2 V; IOUT = 0 mA, device switching 5 mA
ISD Shutdown current into the VIN pin EN = 0 V 0.25 1.5 µA
VUVLO Undervoltage lockout VIN rising 2.85 2.95 3.0 V
Undervoltage lockout VIN falling 2.65 2.75 2.85 V
VUVLO Undervoltage lockout hysteresis 200 mV
CONTROL AND INTERFACE
ILKG EN input leakage current EN = VIN 3 300 nA
VIH;MODE High-level input voltage at the MODE/S-CONF pin 1.0 V
VIL;MODE Low-level input voltage at the MODE/S_CONF pin 0.15 V
VIH High-level input voltage at the EN pin 0.97 1.0 1.03 V
VIL Low-level input voltage at the EN pin 0.87 0.9 0.93 V
VPG Power-good threshold VFB rising, referenced to VFB nominal 93% 96% 99%
VFB falling, referenced to VFB nominal 89% 93% 96%
VPG_HYS Power-good threshold hysteresis  Hysteresis 3%
tPG,DLY Power-good delay time 32 µs
tPG,DLY Power-good pulldown resistance 10 Ω
VPG,OL Low-level output voltage at the PG pin ISINK = 1 mA 0.1 V
IPG,LKG Input leakage current into the PG pin VPG = 5 V 0.01 1 µA
POWER SWITCHES
RDS;ON High-side FET on resistance 250 mΩ
Low-side FET on resistance 85
ILIM High-side FET current limit 1.5 1.8 2.1 A
Low-side FET current limit 1.3 1.6 1.9 A
ILIM;SINK Low-side FET sink current limit 0.8 1 1.2 A
TSD Thermal Shutdown Threshold TJ rising 170 °C
Thermal Shutdown Hysteresis TJ falling 20
fSW Switching frequency 2.5-MHz selection (FPWM mode) 2.5 MHz
fSW Switching frequency 1.0-MHz selection (FPWM mode) 1.0 MHz
TON(MIN) Minimum on time 40 ns
ILKG;SW Leakage current into the SW pin EN = 0 V, VSW = VOS = 5.5 V 0.1 5 µA
OUTPUT
VO Output voltage regulation VSET configuration selected, 0°C ≤ TJ ≤ 85°C –1% +1%
VO Output voltage regulation VSET option selected, –40°C ≤ TJ ≤ 125°C –1.3% +1.1%
VFB Feedback regulation voltage Adjustable configuration selected 0.6 V
VFB Feedback voltage regulation FB option selected, 0°C ≤ TJ ≤ 85°C –0.75% +0.75%
VFB Feedback voltage regulation FB option selected, –40°C ≤ TJ ≤ 125°C –1.1% +0.75%
IFB Input leakage current into FB pin Adjustable configuration, VFB = 0.6 V 1 100 nA
Tdelay Start-up delay time IO = 0 mA, time from EN rising edge until start switching, external FB configuration selected 700 1500 µs
Start-up delay time IO = 0 mA, time from EN rising edge until start switching, VSET configuration selected 1000 1800 µs
TSS Soft-start time IO = 0 mA after Tdelay, from first switching pulse until target VO 600 700 µs
RDISCH Active discharge resistance Discharge = ON - option selected, EN = LOW 7.5 20 Ω