JAJSMS2 March 2022 TPS629210E
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
SUPPLY | ||||||
IQ | Operating quiescent current (power save mode) | IOUT = 0 mA, device not switching | 4 | µA | ||
IQ;PWM | Operating quiescent current (PWM mode) | VIN = 12 V, VOUT = 1.2 V; IOUT = 0 mA, device switching | 5 | mA | ||
ISD | Shutdown current into the VIN pin | EN = 0 V | 0.25 | 3 | µA | |
VUVLO | Undervoltage lockout | VIN rising | 2.85 | 2.95 | 3.0 | V |
Undervoltage lockout | VIN falling | 2.65 | 2.75 | 2.85 | V | |
VUVLO | Undervoltage lockout hysteresis | 200 | mV | |||
CONTROL AND INTERFACE | ||||||
ILKG | EN input leakage current | EN = VIN | 3 | 300 | nA | |
VIH;MODE | High-level input voltage at the MODE/S-CONF pin | 1.0 | V | |||
VIL;MODE | Low-level input voltage at the MODE/S-CONF pin | 0.15 | V | |||
VIH | High-level input voltage at the EN pin | 0.97 | 1.0 | 1.03 | V | |
VIL | Low-level input voltage at the EN pin | 0.87 | 0.9 | 0.93 | V | |
VPG | Power-good threshold | VFB rising, referenced to VFB nominal | 93% | 96% | 99% | |
VFB falling, referenced to VFB nominal | 89% | 93% | 96% | |||
VPG_HYS | Power-good threshold hysteresis | Hysteresis | 3% | |||
tPG,DLY | Power-good delay time | 32 | µs | |||
tPG,DLY | Power-good pulldown resistance | 10 | Ω | |||
VPG,OL | Low-level output voltage at the PG pin | ISINK = 1 mA | 0.1 | V | ||
IPG,LKG | Input leakage current into the PG pin | VPG = 5 V | 0.01 | 1 | µA | |
POWER SWITCHES | ||||||
RDS;ON | High-side FET on resistance | 250 | mΩ | |||
Low-side FET on resistance | 85 | |||||
ILIM | High-side FET current limit | 1.5 | 1.8 | 2.1 | A | |
Low-side FET current limit | 1.3 | 1.6 | 1.9 | A | ||
ILIM;SINK | Low-side FET sink current limit | 0.8 | 1 | 1.2 | A | |
TSD | Thermal shutdown threshold | TJ rising | 170 | °C | ||
Thermal shutdown hysteresis | TJ falling | 20 | ||||
fSW | Switching frequency | 2.5-MHz selection (FPWM mode) | 2.5 | MHz | ||
fSW | Switching frequency | 1.0-MHz selection (FPWM mode) | 1.0 | MHz | ||
TON(MIN) | Minimum on time | 40 | ns | |||
ILKG;SW | Leakage current into the SW pin | EN = 0 V, VSW = VOS = 5.5 V | 0.1 | 5 | µA | |
OUTPUT | ||||||
VO | Output voltage regulation | VSET configuration selected, TJ = 25°C | –0.75% | +0.75% | ||
VO | Output voltage regulation | VSET option selected, –55°C ≤ TJ ≤ 150°C | –1.5% | +1% | ||
VFB | Feedback regulation voltage | Adjustable configuration selected | 0.6 | V | ||
VFB | Feedback voltage regulation | FB option selected, TJ = 25°C | –0.5 % | + 0.5% | ||
VFB | Feedback voltage regulation | FB option selected, –55°C ≤ TJ ≤ 150°C | –1.5% | +0.5% | ||
IFB | Input leakage current into the FB pin | Adjustable configuration, VFB = 0.6 V | 1 | 100 | nA | |
Tdelay | Start-up delay time | IO = 0 mA, time from EN rising edge until start switching, external FB configuration selected | 700 | 1750 | µs | |
Tdelay | Start-up delay time | IO = 0 mA, time from EN rising edge until start switching, VSET configuration selected | 1000 | 2000 | µs | |
TSS | Soft-start time | IO = 0 mA after Tdelay, from first switching pulse until target VO | 600 | 700 | µs | |
RDISCH | Active discharge resistance | Discharge = ON - option selected, EN = LOW | 7.5 | 20 | Ω |