JAJSOG0A october   2022  – march 2023 TPS62993-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Mode Selection and Device Configuration MODE/S-CONF
      2. 8.3.2  Adjustable VO Operation (External Voltage Divider)
      3. 8.3.3  Selectable VO Operation (VSET and Internal Voltage Divider)
      4. 8.3.4  Soft Start and Tracking (SS/TR)
        1. 8.3.4.1 Tracking Function
      5. 8.3.5  Smart Enable with Precise Threshold
      6. 8.3.6  Power Good (PG)
      7. 8.3.7  Output Discharge Function
      8. 8.3.8  Undervoltage Lockout (UVLO)
      9. 8.3.9  Current Limit and Short-Circuit Protection
      10. 8.3.10 High Temperature Specifications
      11. 8.3.11 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Forced Pulse Width Modulation (FPWM) Operation
      2. 8.4.2 Power Save Mode Operation (Auto PFM and PWM)
      3. 8.4.3 AEE (Automatic Efficiency Enhancement)
      4. 8.4.4 100% Duty-Cycle Operation
      5. 8.4.5 Starting into a Prebiased Load
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application with Adjustable Output Voltage
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Custom Design With WEBENCH® Tools
        2. 9.2.2.2 Programming the Output Voltage
        3. 9.2.2.3 External Component Selection
          1. 9.2.2.3.1 Output Filter and Loop Stability
          2. 9.2.2.3.2 Inductor Selection
          3. 9.2.2.3.3 Capacitor Selection
            1. 9.2.2.3.3.1 Output Capacitor
            2. 9.2.2.3.3.2 Input Capacitor
            3. 9.2.2.3.3.3 Soft-Start Capacitor
      3. 9.2.3 Application Curves
        1. 9.2.3.1 Application Curves Vout = 1.8 V
        2. 9.2.3.2 Application Curves Vout = 1.2 V
        3. 9.2.3.3 Application Curves Vout = 0.6 V
    3. 9.3 Typical Application with Selectable VOUT using VSET
      1. 9.3.1 Design Requirements
      2. 9.3.2 Detailed Design Procedure
        1. 9.3.2.1 Programming the Output Voltage
      3. 9.3.3 Application Curves
        1. 9.3.3.1 Application Curves Vout = 5 V
        2. 9.3.3.2 Application Curves Vout = 3.3 V
    4. 9.4 System Examples
      1. 9.4.1 LED Power Supply
      2. 9.4.2 Powering Multiple Loads
      3. 9.4.3 Voltage Tracking
      4. 9.4.4 Inverting Buck-Boost (IBB)
    5. 9.5 Power Supply Recommendations
    6. 9.6 Layout
      1. 9.6.1 Layout Guidelines
      2. 9.6.2 Layout Example
      3. 9.6.3 Thermal Considerations
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 サード・パーティ製品に関する免責事項
      2. 10.1.2 Development Support
        1. 10.1.2.1 Custom Design With WEBENCH® Tools
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 ドキュメントの更新通知を受け取る方法
    4. 10.4 サポート・リソース
    5. 10.5 Trademarks
    6. 10.6 静電気放電に関する注意事項
    7. 10.7 用語集
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.4.4 Inverting Buck-Boost (IBB)

The need to generate negative voltage rails for electronic designs is a common challenge. The wide 3-V to 10-V input voltage range of the TPS62993-Q1 makes it ideal for an inverting buck-boost (IBB) circuit, where the output voltage is inverted or negative with respect to ground.

The circuit operation in the IBB topology differs from that in the traditional buck topology. Though the components are connected the same as with a traditional buck converter, the output voltage terminals are reversed. See Figure 9-86.

The maximum input voltage that can be applied to an IBB converter is less than the maximum voltage that can be applied to the TPS62993-Q1 in a typical buck configuration. This is because the ground pin of the IC is connected to the (negative) output voltage. Therefore, the input voltage across the device is VIN to VOUT, and not VIN to ground. Thus, the input voltage range of the TPS62993-Q1 in an IBB configuration becomes 3 V to 10 V + VOUT, where VOUT is a negative value.

The output voltage range is the same as when configured as a buck converter, but only negative. Thus, the output voltage for a TPS62993-Q1 in an IBB configuration can be set between –0.4 V and –5.5 V.

The maximum output current for the TPS62993-Q1 in an IBB topology is normally lower than a traditional buck configuration due to the average inductor current being higher in an IBB configuration. Traditionally, lower input or (more negative) output voltages results in a lower maximum output current. However, using a larger inductor value or the higher 2.5-MHz frequency setting can be used to recover some or all of this lost maximum current capability.

When implementing an IBB design, it is important to understand that the IC ground is tied to the negative voltage rail, and in turn, the electrical characteristics of the TPS62993-Q1 device are referenced to this rail. During power up, as there is no charge in the output capacitor and the IC GND pin (and VOUT) are effectively 0 V, thus parameters such as the VIN UVLO and EN thresholds are the same as in a typical buck configuration. However, after the output voltage is in regulation, due to the negative voltage on the IC GND pin, the device traditionally continues to operate below what can appear to be the normal UVLO or EN falling thresholds relative to the system ground. Take care if the user is using the dynamic mode change feature on the MODE pin of the TPS62993-Q1 or driving the EN pin from an upstream microcontroller as the high and low thresholds are relative to the negative rail and not the system ground.

More information on using a DCS regulator in an IBB configuration can be found in the Description Compensating the Current Mode Boost Control Loop, Using the TPS6215x in an Inverting Buck-Boost Topology, and Using the TPS629210 in an Inverting Buck-Boost Topology application notes.

GUID-20220421-SS0I-DBRS-SZDL-LCZ1MQ389CRV-low.svg Figure 9-86 IBB Example with Adjustable Feedback
Note: Figure 9-86 shows an external feedback configuration, but the internal (VSET) configuration can also be used.