JAJSQ85C november 2011 – september 2020 TPS63060 , TPS63061
PRODUCTION DATA
Connecting a clock signal at PS/SYNC forces the device to synchronize to the connected clock frequency.
Synchronization is done by a PLL to lower and higher frequencies compared to the internal clock. The PLL can also tolerate missing clock pulses without the converter malfunctioning. The PS/SYNC input supports standard logic thresholds.