JAJSGI0D November   2018  – January 2021 TPS63802

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 概要 (続き)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Control Loop Description
      2. 9.3.2  Precise Device Enable: Threshold- or Delayed Enable
      3. 9.3.3  Mode Selection (PFM/PWM)
      4. 9.3.4  Undervoltage Lockout (UVLO)
      5. 9.3.5  Soft Start
      6. 9.3.6  Adjustable Output Voltage
      7. 9.3.7  Overtemperature Protection - Thermal Shutdown
      8. 9.3.8  Input Overvoltage - Reverse-Boost Protection (IVP)
      9. 9.3.9  Output Overvoltage Protection (OVP)
      10. 9.3.10 Power-Good Indicator
    4. 9.4 Device Functional Modes
      1. 9.4.1 Peak-Current Mode Architecture
        1. 9.4.1.1 Reverse Current Operation, Negative Current
        2. 9.4.1.2 Boost Operation
        3. 9.4.1.3 Buck-Boost Operation
        4. 9.4.1.4 Buck Operation
      2. 9.4.2 Power Save Mode Operation
        1. 9.4.2.1 Current Limit Operation
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Custom Design With WEBENCH® Tools
        2. 10.2.2.2 Inductor Selection
        3. 10.2.2.3 Output Capacitor Selection
        4. 10.2.2.4 Input Capacitor Selection
        5. 10.2.2.5 Setting The Output Voltage
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
      2. 13.1.2 Development Support
        1. 13.1.2.1 Custom Design With WEBENCH® Tools
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 ドキュメントの更新通知を受け取る方法
    4. 13.4 サポート・リソース
    5. 13.5 Trademarks
    6. 13.6 静電気放電に関する注意事項
    7. 13.7 用語集
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.5 Electrical Characteristics

VIN= 1.8 V to 5.5 V, VOUT = 1.8 V to 5.2  V , TJ= –40°C to +125°C, typical values are at VIN= 3.6 V, VOUT = 3.3 V  and TJ= 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY 
VIN;LOAD Minimum input voltage for full load, once started IOUT = 2 A, VOUT = 3.3 V, TJ = 25°C 2.3 V
IQ;VIN Quiescent current into VIN TPS63802; TJ = 25°C, EN = VIN = 3.6 V, VOUT = 3.3 V, not switching 11 μA
ISD Shutdown current into VIN EN = low, -40°C ≤ TJ ≤ 85°C, VIN = 3.6 V, VOUT = 0 V 45 600 nA
UVLO Undervoltage lockout threshold VIN falling, VOUT ≥ 1.8 V, once started 1.2 1.25 1.29 V
Undervoltage lockout threshold VIN rising 1.6 1.7 1.79 V
TSD Thermal shutdown Temperature rising 150 °C
TSD;HYST Thermal shutdown hysteresis 20 °C
SOFT-START, POWER GOOD
Tramp  Soft-start, Current limit ramp time TJ = 25°C,  VIN = 3.6 V, VOUT = 3.3 V, IO = 3.5 A, time from first switching to power good 224 µs
Tdelay  Delay from EN-edge until rising VOUT TJ = 25°C,  VIN = 3.6 V, VOUT = 3.3 V, Delay from EN-edge until rising
first switching		 321 µs
LOGIC SIGNALS EN, MODE
VTHR;EN Threshold Voltage rising for EN-Pin 1.07 1.1 1.13 V
VTHF;EN Threshold Voltage falling for EN-Pin 0.97 1 1.03 V
VIH High-level input voltage 1.2 V
VIL Low-level input voltage 0.4 V
VPG;rising Power Good threshold voltage VOUT rising, referenced to VOUT nominal 95 %
VPG;falling VOUT falling, referenced to VOUT nominal 90 %
VPG;Low Power Good low-level output voltage ISINK = 1 mA 0.4 V
tPG;delay  Power Good delay time VFB falling 14 µs
Ilkg Input leakage current 0.01 0.2 µA
OUTPUT
ISD Shutdown current into VOUT EN = low, -40°C ≤ TJ ≤ 85°C, VIN = 3.6 V, VOUT = 3.3 V ±0.5 ±600 nA
VFB Feedback Regulation Voltage 500 mV
VFB Feedback Voltage accuracy PWM mode –1 1 %
    Overvoltage Protection Threshold  VOUT rising  5.5 5.7 5.9 V
VIN rising  5.5 5.7 5.9 V
IPWM/PFM  Peak Inductor Current to enter PFM-Mode VIN = 3.6 V; VOUT = 3.3 V 1.06 A
IFB Feedback Input Bias Current VFB = 500 mV 5 100 nA
IPK     Peak Current Limit, Boost Mode TPS63802; VIN ≥ 2.5 V 4 5 5.75 A
Peak Current Limit, Buck-Boost Mode 5 A
Peak Current Limit, Buck Mode 3.8 A
IPK;Reverse Peak Current Limit for Reverse Operation VI = 5 V, VO = 3.3 V –0.9 A
Buck RDS;ON  High-side FET on-resistance VIN = 3 V, VOUT = 3.3 V; I(L2) = 0.19 A VIN = 3 V, VOUT = 3.3 V; IO = 0.5 A 47 mΩ
Low-side FET on-resistance VIN = 3 V, VOUT = 3.3 V; I(L2) = 0.19 A VIN = 3 V, VOUT = 3.3 V; IO = 0.5 A 30 mΩ
Boost RDS;ON High-side FET on-resistance VIN = 3 V, VOUT = 3.3 V; I(L1) = 0.19 A VIN = 3 V, VOUT = 3.3 V; IO = 0.5 A 43 mΩ
Low-side FET on-resistance VIN = 3 V, VOUT = 3.3 V; I(L1) = 0.19 A VIN = 3 V, VOUT = 3.3 V; IO = 0.5 A 18 mΩ
fSW   Inductor Switching Frequency, Boost Mode VIN = 2.3V, VOUT = 3.3V, no Load, MODE = HIGH, TJ = 25°C 2.1 MHz
Inductor Switching Frequency, Buck-Boost Mode VIN = 3.3V, VOUT = 3.3V, no Load, MODE = HIGH, TJ = 25°C 1.4 MHz
Inductor Switching Frequency, Buck Mode VIN = 4.3, VOUT = 3.3V, no Load, MODE = HIGH, TJ = 25°C 1.6 MHz
Line regulation VIN = 2.4 V to 5.5 V, VOUT = 3.3V, IOUT = 2 A 0.3 %
Load regulation VIN= 3.6 V, VOUT = 3.3V, IOUT = 0 A to 2 A, forced-PWM mode 0.1 %