JAJSHB0 April   2019 TPS650002-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      代表的なアプリケーションの回路図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Step-Down Converter
      2. 7.3.2 Soft Start
      3. 7.3.3 Linear Regulators
      4. 7.3.4 Power Good
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Output Filter Design (Inductor and Output Capacitor)
          1. 8.2.2.1.1 Inductor Selection
          2. 8.2.2.1.2 Output Capacitor Selection
        2. 8.2.2.2 Input Capacitor Selection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 11.2 ドキュメントのサポート
      1. 11.2.1 関連資料
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 コミュニティ・リソース
    5. 11.5 商標
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.1 Step-Down Converter

The step-down converter is intended to allow maximum flexibility in the end equipment. Figure 16 shows the necessary connections.

TPS650002-Q1 Fixed-DCDC.gifFigure 16. DC-DC Converter Block Diagram

Externally adjustable output voltages and additional current-limit options are also possible. Contact TI for further information.

The step-down converter has two modes of operation to maximize efficiency at different load conditions. At moderate to heavy load currents, the device operates in a fixed-frequency pulse-width modulation (PWM) mode that results in small output ripple and high efficiency. Pulling the MODE pin to a DC-high level results in PWM mode over the entire load range.

At light load currents, the device operates in a pulsed frequency-modulation (PFM) mode to improve efficiency. The transition to this mode occurs when the inductor current through the low-side FET becomes zero, indicating discontinuous conduction. PFM mode also results in the output voltage increasing by 1% from the PWM mode value. This voltage positioning is intended to minimize both the voltage undershoot of a load step from light to heavy loads, as when a processor moves from sleep to active modes, and the voltage overshoot at load removal. shows the voltage positioning behavior for a light-to-heavy load step.

TPS650002-Q1 pwr_sav_md_lvs810.gifFigure 17. PFM Voltage Positioning

Pulling the MODE pin to DC ground results in an automatic transition between PFM and PWM modes to maximize efficiency.

The DC-DC converter output automatically discharges to ground through an internal 450-Ω load when EN_DCDC goes low or when the UVLO condition is met.