JAJSQ20 May   2024 TPS650362-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1特長
  3. 2アプリケーション
  4. 3概要
  5. 4Pin Configuration and Functions
  6. 5Device and Documentation Support
    1. 5.1 Device Support
      1. 5.1.1 サード・パーティ製品に関する免責事項
    2. 5.2 ドキュメントの更新通知を受け取る方法
    3. 5.3 サポート・リソース
    4. 5.4 Trademarks
    5. 5.5 静電気放電に関する注意事項
    6. 5.6 用語集
  7. 6Revision History
  8. 7Mechanical, Packaging, and Orderable Information
    1. 7.1 Package Option Addendum
    2. 7.2 Tape and Reel Information
    3.     18

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
  • RAY|24
サーマルパッド・メカニカル・データ
発注情報

Pin Configuration and Functions

TPS650360-Q1 TPS650361-Q1 TPS650362-Q1  TPS650363-Q1 TPS650365-Q1 TPS650366-Q1 TPS65036x-Q1 24-Pin QFN (Top View) Figure 4-1 TPS65036x-Q1 24-Pin QFN (Top View)
Table 4-1 Pin Functions
PIN I/O TYPE DESCRIPTION CONNECTION IF NOT USED
NO. NAME
1 VLDO O Analog LDO Output Voltage. When LDO is not used, this pin can be used for monitoring an external rail. When LDO and corresponding monitoring are both deactivated in NVM pin can be left floating. Floating
2 AGND Ground Analog Ground Not applicable
3 VDD_1P8 PWR Analog Internal Reference Voltage - For Internal Use Only Not applicable
4 PGND Ground Power Ground. Not applicable
5 FB_B1 I Analog BUCK1 (Wide VinStep-Down Converter) Feedback. When BUCK1 is deactivated in NVM pin can be left floating. Floating
6 NRSTOUT O Digital Reset Output Floating
7 BOOT I PWR BOOTCAP pin for BUCK1 (Wide Vin Step-Down Converter) Floating
8 LX_B1 Analog BUCK1 (Wide Vin Step-Down Converter) Switch Node. When BUCK1 is deactivated in NVM pin can be left floating. Floating
9 VSYS/PVIN_B1 I Power

Device Input Power and Input Voltage for BUCK1 (Wide Vin Step-Down Converter)

Input supply
10 SEQ I Digital Enable and Sequence Control Input Floating
11 VREG O Power Gate Drive LDO Output for BUCK1 (Wide Vin Step Down Converter) Not applicable
12 FB_B3 I Analog BUCK3 (Low Voltage Step-Down Converter) Feedback. When BUCK3 is not used, this pin can be used for monitoring an external rail. When BUCK3 and corresponding monitoring are both deactivated in NVM pin can be left floating. Floating
13 GPIO I Digital General Purpose Input to Sequencer. Floating
I Digital Alternative programmable function: Trigger Mode Watchdog Input
O Digital Alternative programmable function: General Purpose Output
I Digital Alternative programmable function: MCU Error Signal Monitoring Input (nERR)
I Analog Alternative programmable function: Watchdog Disable Input.
14 PVIN_B3 I Power

BUCK3 (Low Voltage Step-Down Converter) Input Voltage. PVIN_B2 and PVIN_B3 must be tied together and voltage applied at the same time or after the voltage on VSYS/PVIN_B1 is applied.

Input supply
15 LX_B3 O Power BUCK3 (Low Voltage Step-Down Converter) Switch Node. Floating
16 PGND Ground Power Ground. Not applicable
17 LX_B2 O Power BUCK2 (Low Voltage Step-Down Converter) Switch Node Floating
18 PVIN_B2 I Power

BUCK2 (Low Voltage Step-Down Converter) Input Voltage. PVIN_B2 and PVIN_B3 must be tied together and voltage applied at the same time or after the voltage on VSYS/PVIN_B1 is applied.

Input supply
19 VIO I Power IO Supply Voltage pin. Not applicable
20 FB_B2 I Analog BUCK2 (Low Voltage Step-Down Converter) Feedback. When BUCK2 is not used, this pin can be used for monitoring an external rail. When BUCK2 and corresponding monitoring are both deactivated in NVM pin can be left floating. Floating
21 nINT/GPIO O Digital Interrupt output Floating
I Digital Alternative programmable function: Trigger Mode Watchdog Input
I Digital Alternative programmable function: Control Input for Entering and Exiting Low Power Mode
22 SDA I/O Ground I2C interface bidirectional serial data (external pull up). Pull high
23 SCL I Power I2C interface serial clock (external pull up). Pull high
24 PVIN_LDO I Power

LDO Input Voltage. Apply the voltage on PVINLDO at the same time or after the voltage on VSYS is applied.

Input supply