JAJSFE6I July 2009 – May 2018 TPS65070 , TPS65072 , TPS65073 , TPS650731 , TPS650732
UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.
The TPS6507x contain circuitry that can generate a reset pulse for a processor with a certain delay time. The input voltage at a comparator is sensed at an input called THRESHOLD. When the voltage exceeds the threshold, the output goes high with the delay time defined in register PGOOD. The reset circuitry is not active in OFF-state. The pullup resistor for this open-drain output must not be connected directly to the battery as this may cause a leakage path when the power path (SYS voltage) is turned off. The reset delay time equals the setting for the PGOOD signal. For devices that are configured with EN_wLED input, the reset output should be left open.