JAJSFE6I July 2009 – May 2018 TPS65070 , TPS65072 , TPS65073 , TPS650731 , TPS650732
UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
VVINDCDC2 | Input voltage range | Connected to SYS pin | 2.8 | 6.3 | V | ||
IO | Maximum output current | TPS65072/73/731/732 | Vin > 2.8 V | 600 | mA | ||
TPS65070 | 1500 | ||||||
RDS(ON) | High side MOSFET ON-resistance | VINDCDC2 = 2.8 V | 150 | 300 | mΩ | ||
VINDCDC2 = 3.5 V | 120 | 200 | |||||
ILH | High side MOSFET leakage current | VINDCDC2 = 6.3 V | 2 | µA | |||
RDS(ON) | Low side MOSFET ON-resistance | VINDCDC2 = 2.8 V | 200 | 300 | mΩ | ||
VINDCDC2 = 3.5 V | 160 | 180 | |||||
ILL | Low side MOSFET leakage current | VDS = 6.3 V | 1 | µA | |||
ILIMF | Forward current limit | TPS65072/73/731/732 | 2.8 V < VINDCDC2 < 6.3 V | 0.8 | 1.1 | 1.5 | A |
TPS65070 | 2.1 | 2.4 | 3.5 | ||||
fS | Oscillator frequency | 1.95 | 2.25 | 2.55 | MHz | ||
Vout | Adjustable output voltage range | External resistor divider | 0.6 | Vin | V | ||
Vref | Reference voltage | 600 | mV | ||||
Vout | Fixed output voltage range | Internal resistor divider, I2C selectable (Default setting) | 0.725 | 3.3 | V | ||
Vout | Default output voltage for TPS65070, TPS650732, | For DEFDCDC2 = LOW | 1.8 | V | |||
For DEFDCDC2 = HIGH | 3.3 | ||||||
Default output voltage for TPS65072 | For DEFDCDC2 = LOW | 1.8 | |||||
For DEFDCDC2 = HIGH | 2.5 | ||||||
Vout | Default output voltage for TPS65073, TPS650731 | For DEFDCDC2 = LOW | 1.2 | V | |||
For DEFDCDC2 = HIGH | 1.8 | ||||||
Vout | DC output voltage accuracy; PFM mode (1) | VINDCDC2 = 2.8 V to 6.3 V;
0 mA = IO = 1.5 A |
–2% | 3% | |||
DC output voltage accuracy; PWM mode (1) | –1.5% | 1.5% | |||||
DC output voltage accuracy with resistor divider at DEFDCDC2; PFM | VINDCDC2 = VDCDC2 +0.3 V (min 2.8 V) to 6.3 V; 0 mA = IO = 1.5A | –2% | 3% | ||||
DC output voltage accuracy with resistor divider at DEFDCDC2; PWM | –1% | 1% | |||||
ΔVOUT | Power save mode ripple voltage | IOUT = 1 mA, PFM mode(2) | 40 | mVpp | |||
tStart | Start-up time | Time from active EN to Start switching | 170 | µs | |||
tRamp | VOUT ramp up time | Time to ramp from 5% to 95% of VOUT | 250 | µs | |||
Power good threshold | rising voltage | Vo - 5% | |||||
Power good threshold | falling voltage | Vo - 10% | |||||
RDIS | Internal discharge resistor at L2 | –35% | 250 | 35% | Ω |