JAJSFE6I July 2009 – May 2018 TPS65070 , TPS65072 , TPS65073 , TPS650731 , TPS650732
UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.
LDO_CTRL1 | B7 | B6 | B5 | B4 | B3 | B2 | B1 | BO |
---|---|---|---|---|---|---|---|---|
Bit name and function | LDO_SQ2 | LDO_SQ1 | LDO_SQ0 | LDO1[3] | LDO1[2] | LDO1[1] | LDO1[0] | |
Default for
–70 |
See Table 10 | See Table 10 | See Table 10 | 0 | 1 | 0 | 0 | 1 |
Default for
–73, –731, –732, |
See Table 10 | See Table 10 | See Table 10 | 0 | 1 | 0 | 0 | 1 |
Default for
–72 |
See Table 10 | See Table 10 | See Table 10 | 0 | 0 | 0 | 1 | 0 |
Default value loaded by: | UVLO | UVLO | UVLO | UVLO | UVLO | UVLO | UVLO | |
Read/write | R/W | R/W | R/W | R | R/W | R/W | R/W | R/W |
Bit 7..5 | LDO_SQ2 to LDO_SQ0: power-up sequencing: (power down sequencing is the reverse) |
000 = LDO1 and LDO2 are enabled as soon as device is in ON-state by pulling PB_IN=LOW or POWER_ON=HIGH | |
001 = LDO1 and LDO2 are enabled after DCDC3 was enabled and its power good Bit is high. | |
010 = external pin at “EN_EXTLDO” is driven HIGH first, after >1ms LDO2 is enabled, LDO1 is enabled at the same time with DCDC3. EN_EXTLDO is driven LOW by going into OFF-state, LDO2 is disabled at the same time with EN_EXTLDO going LOW. Disabling LDO2 in register CON_CTRL1 will not drive EN_EXTLDO=LOW. (Atlas4) | |
011 = LDO1 is enabled 300us after PGOOD of DCDC1, LDO2 is off. LDO2 can be enabled/disabled by an I2C command in register CON_CTRL1. | |
100 = LDO1 is enabled after DCDC1 shows power good; LDO2 is enabled with DCDC3 | |
101 = LDO1 is enabled with DCDC2; LDO2 is enabled after DCDC1 is enabled and its power good Bit is high | |
110 = LDO1 is enabled 10ms after DCDC2 is enabled and its power good Bit is high, LDO2 is off. LDO2 can be enabled / disabled by an I2C command in register CON_CTRL1. | |
111 = external pin at EN_EXTLDO is driven HIGH first, after >1ms LDO2 is enabled, LDO1 is enabled when EN_DCDC3 pin is pulled high AND DCDC3 is power good (first power–up from OFF state). LDO1 is disabled when EN_DCDC3 pin goes LOW for SLEEP mode. LDO2 is disabled at the same time with DCDC2 and DCDC1 during shutdown (Sirf PRIMA). | |
Automatic sequencing sets the enable Bits of the LDOs accordingly, so the LDOs can be enabled or disabled by the I2C interface in ON-state. | |
All sequencing options that define a ramp in sequence for the DC-DC converters and the LDOs, (not at the same time) are timed such that the power good signal triggers the start for the next converter. If there is a time defined such as 1-ms delay, the timer is started after the power good signal of the previous converter is high. LDO enable is delayed by 170 µs internally to match the delay for the DC-DC converters. By this, for sequencing options that define a ramp at the same time for an LDO and a DC-DC converter, it is made sure they will ramp at the same time, given the fact the DC-DC converters have an internal 170-µs delay as well. | |
Bit 3..0 | LDO1(3) to LDO1(0):
The Bits define the default output voltage of LDO1 according to the table below: |
LDO1[3] | LDO1[2] | LDO1[1] | LDO1[0] | LDO1 OUTPUT VOLTAGE |
---|---|---|---|---|
0 | 0 | 0 | 0 | 1.0 V |
0 | 0 | 0 | 1 | 1.1 V |
0 | 0 | 1 | 0 | 1.2 V |
0 | 0 | 1 | 1 | 1.25 V |
0 | 1 | 0 | 0 | 1.3 V |
0 | 1 | 0 | 1 | 1.35 V |
0 | 1 | 1 | 0 | 1.4 V |
0 | 1 | 1 | 1 | 1.5 V |
1 | 0 | 0 | 0 | 1.6 V |
1 | 0 | 0 | 1 | 1.8 V |
1 | 0 | 1 | 0 | 2.5 V |
1 | 0 | 1 | 1 | 2.75 V |
1 | 1 | 0 | 0 | 2.8 V |
1 | 1 | 0 | 1 | 3.0 V |
1 | 1 | 1 | 0 | 3.1 V |
1 | 1 | 1 | 1 | 3.3 V |