SWCS128A March   2015  – December 2015

PRODUCTION DATA.  

  1. 1 Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2 Revision History
  3. 3 Pin Configuration and Functions
  4. 4 Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  Thermal Information
    5. 4.5  Electrical Characteristics: Total Current Consumption
    6. 4.6  Electrical Characteristics: Reference and Monitoring System
    7. 4.7  Electrical Characteristics: Buck Controllers
    8. 4.8  Electrical Characteristics: Synchronous Buck Converters
    9. 4.9  Electrical Characteristics: LDOs
    10. 4.10 Electrical Characteristics: Load Switches
    11. 4.11 Digital Signals: I2C Interface
    12. 4.12 Digital Input Signals (CTLx)
    13. 4.13 Digital Output Signals (IRQB, GPOx)
    14. 4.14 Timing Requirements
    15. 4.15 Switching Characteristics
    16. 4.16 Typical Characteristics
  5. 5 Detailed Description
    1. 5.1 Overview
    2. 5.2 Functional Block Diagram
    3. 5.3 SMPS Voltage Regulators
      1. 5.3.1 Controller Overview
      2. 5.3.2 Converter Overview
      3. 5.3.3 DVS
      4. 5.3.4 Decay
      5. 5.3.5 Current Limit
    4. 5.4 LDOs and Load Switches
      1. 5.4.1 VTT LDO
      2. 5.4.2 LDOA1-LDOA3
      3. 5.4.3 Load Switches
    5. 5.5 Power Goods (PGOOD or PG) and GPOs
    6. 5.6 Power Sequencing and VR Control
      1. 5.6.1 CTLx Sequencing
      2. 5.6.2 PG Sequencing
      3. 5.6.3 Enable Delay
      4. 5.6.4 Power Up Sequence
      5. 5.6.5 Power Down Sequence
      6. 5.6.6 Sleep State Entry and Exit
      7. 5.6.7 Emergency Shutdown
    7. 5.7 Device Functional Modes
      1. 5.7.1 Off Mode
      2. 5.7.2 Standby Mode
      3. 5.7.3 Active Mode
    8. 5.8 I2C Interface
      1. 5.8.1 F/S-Mode Protocol
    9. 5.9 Register Maps
      1. 5.9.1  Register Map Summary
      2. 5.9.2  DEVICEID: PMIC Device and Revision ID Register (offset = 1h) [reset = OTP-Programmable]
      3. 5.9.3  IRQ: PMIC Interrupt Register (offset = 2h) [reset = 0000 0000]
      4. 5.9.4  IRQ_MASK: PMIC Interrupt Mask Register (offset = 3h) [reset = 1111 1111]
      5. 5.9.5  PMICSTAT: PMIC Status Register (offset = 4h) [reset = 0000 0000]
      6. 5.9.6  SHUTDNSRC: PMIC Shut-Down Event Register (offset = 5h) [reset = 0000 0000]
      7. 5.9.7  BUCK1CTRL: BUCK1 Control Register (offset = 20h) [reset = OTP-Programmable]
      8. 5.9.8  BUCK2CTRL: BUCK2 Control Register (offset = 21h) [reset = OTP-Programmable]
      9. 5.9.9  BUCK3DECAY: BUCK3 Decay Control Register (offset = 22h) [reset = OTP-Programmable]
      10. 5.9.10 BUCK3VID: BUCK3 VID Register (offset = 23h) [reset = OTP-Programmable]
      11. 5.9.11 BUCK3SLPCTRL: BUCK3 Sleep Control VID Register (offset = 24h) [reset = OTP-Programmable]
      12. 5.9.12 BUCK4CTRL: BUCK4 Control Register (offset = 25h) [reset = OTP-Programmable]
      13. 5.9.13 BUCK5CTRL: BUCK5 Control Register (offset = 26h) [reset = OTP-Programmable]
      14. 5.9.14 BUCK6CTRL: BUCK6 Control Register (offset = 27h) [reset = OTP-Programmable]
      15. 5.9.15 LDOA2CTRL: LDOA2 Control Register (offset = 28h) [reset = OTP-Programmable]
      16. 5.9.16 LDOA3CTRL: LDOA3 Control Register (offset = 29h) [reset = OTP-Programmable]
      17. 5.9.17 DISCHCTRL1: Discharge Control1 Register (offset = 40h) [reset = OTP-Programmable]
      18. 5.9.18 DISCHCTRL2: Discharge Control2 Register (offset = 41h) [reset = OTP-Programmable]
      19. 5.9.19 DISCHCTRL3: Discharge Control3 Register (offset = 42h) [reset = OTP-Programmable]
      20. 5.9.20 PG_DELAY1: Power Good Delay1 Register (offset = 43h) [reset = OTP-Programmable]
      21. 5.9.21 FORCESHUTDN: Force Emergency Shutdown Control Register (offset = 91h) [reset = 0000 0000]
      22. 5.9.22 BUCK1SLPCTRL: BUCK1 Sleep Control Register (offset = 92h) [reset = OTP-Programmable]
      23. 5.9.23 BUCK2SLPCTRL: BUCK2 Sleep Control Register (offset = 93h) [reset = OTP-Programmable]
      24. 5.9.24 BUCK4VID: BUCK4 VID Register (offset = 94h) [reset = OTP-Programmable]
      25. 5.9.25 BUCK4SLPVID: BUCK4 Sleep VID Register (offset = 95h) [reset = OTP-Programmable]
      26. 5.9.26 BUCK5VID: BUCK5 VID Register (offset = 96h) [reset = OTP-Programmable]
      27. 5.9.27 BUCK5SLPVID: BUCK5 Sleep VID Register (offset = 97h) [reset = OTP-Programmable]
      28. 5.9.28 BUCK6VID: BUCK6 VID Register (offset = 98h) [reset = OTP-Programmable]
      29. 5.9.29 BUCK6SLPVID: BUCK6 Sleep VID Register (offset = 99h) [reset = OTP-Programmable]
      30. 5.9.30 LDOA2VID: LDOA2 VID Register (offset = 9Ah) [reset = OTP-Programmable]
      31. 5.9.31 LDOA3VID: LDOA3 VID Register (offset = 9Bh) [reset = OTP-Programmable]
      32. 5.9.32 BUCK123CTRL: BUCK1-3 Control Register (offset = 9Ch) [reset = OTP-Programmable]
      33. 5.9.33 PG_DELAY2: Power Good Delay2 Register (offset = 9Dh) [reset = OTP-Programmable]
      34. 5.9.34 SWVTT_DIS: SWVTT Disable Register (offset = 9Fh) [reset = OTP-Programmable]
      35. 5.9.35 I2C_RAIL_EN1: VR Pin Enable Override1 Register (offset = A0h) [reset = OTP-Programmable]
      36. 5.9.36 I2C_RAIL_EN2/GPOCTRL: VR Pin Enable Override2/GPO Control Register (offset = A1h) [reset = OTP-Programmable]
      37. 5.9.37 PWR_FAULT_MASK1: VR Power Fault Mask1 Register (offset = A2h) [reset = OTP-Programmable]
      38. 5.9.38 PWR_FAULT_MASK2: VR Power Fault Mask2 Register (offset = A3h) [reset = OTP-Programmable]
      39. 5.9.39 GPO1PG_CTRL1: GPO1 PG Control1 Register (offset = A4h) [reset = OTP-Programmable]
      40. 5.9.40 GPO1PG_CTRL2: GPO1 PG Control2 Register (offset = A5h) [reset = OTP-Programmable]
      41. 5.9.41 GPO4PG_CTRL1: GPO4 PG Control1 Register (offset = A6h) [reset = OTP-Programmable]
      42. 5.9.42 GPO4PG_CTRL2: GPO4 PG Control2 Register (offset = A7h) [reset = OTP-Programmable]
      43. 5.9.43 GPO2PG_CTRL1: GPO2 PG Control1 Register (offset = A8h) [reset = OTP-Programmable]
      44. 5.9.44 GPO2PG_CTRL2: GPO2 PG Control2 Register (offset = A9h) [reset = OTP-Programmable]
      45. 5.9.45 GPO3PG_CTRL1: GPO3 PG Control1 Register (offset = AAh) [reset = OTP-Programmable]
      46. 5.9.46 GPO3PG_CTRL2: GPO3 PG Control2 Register (offset = ABh) [reset = OTP-Programmable]
      47. 5.9.47 MISCSYSPG Register (offset = ACh) [reset = OTP-Programmable]
      48. 5.9.48 LDOA1CTRL: LDOA1 Control Register (offset = AEh) [reset = OTP-Programmable]
      49. 5.9.49 PG_STATUS1: Power Good Status1 Register (offset = B0h) [reset = 0000 0000]
      50. 5.9.50 PG_STATUS2: Power Good Status2 Register (offset = B1h) [reset = 0000 0000]
      51. 5.9.51 PWR_FAULT_STATUS1: Power Fault Status1 Register (offset = B2h) [reset = 0000 0000]
      52. 5.9.52 PWR_FAULT_STATUS2: Power Fault Status2 Register (offset = B3h) [reset = 0000 0000]
      53. 5.9.53 TEMPCRIT: Temperature Fault Status Register (offset = B4h) [reset = 0000 0000]
      54. 5.9.54 TEMPHOT: Temperature Hot Status Register (offset = B5h) [reset = 0000 0000]
      55. 5.9.55 OC_STATUS: Overcurrent Fault Status Register (offset = B6h) [reset = 0000 0000]
  6. 6 Application and Implementation
    1. 6.1 Application Information
      1. 6.1.1 Typical Application
        1. 6.1.1.1 Design Requirements
        2. 6.1.1.2 Detailed Design Procedure
          1. 6.1.1.2.1 Controller Design Procedure
            1. 6.1.1.2.1.1 Selecting the Inductor
            2. 6.1.1.2.1.2 Selecting the Output Capacitors
            3. 6.1.1.2.1.3 Selecting the FETs
            4. 6.1.1.2.1.4 Bootstrap Capacitor
            5. 6.1.1.2.1.5 Setting the Current Limit
            6. 6.1.1.2.1.6 Selecting the Input Capacitors
          2. 6.1.1.2.2 Converter Design Procedure
            1. 6.1.1.2.2.1 Selecting the Inductor
            2. 6.1.1.2.2.2 Selecting the Output Capacitors
            3. 6.1.1.2.2.3 Selecting the Input Capacitors
          3. 6.1.1.2.3 LDO Design Procedure
        3. 6.1.1.3 Application Curves
    2. 6.2 VIN 5-V Application
      1. 6.2.1 Design Requirements
      2. 6.2.2 Design Procedure
        1. 6.2.2.1 Controller Design Procedure
          1. 6.2.2.1.1 Selecting the LC Output Filter
          2. 6.2.2.1.2 Selecting the FETs
          3. 6.2.2.1.3 Setting the Current Limit
          4. 6.2.2.1.4 Selecting the Input Capacitors
      3. 6.2.3 Application Curve
    3. 6.3 Do's and Don'ts
  7. 7 Power Supply Coupling and Bulk Capacitors
  8. 8 Layout
    1. 8.1 Layout Guidelines
    2. 8.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
      2. 9.1.2 Development Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Community Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  10. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Package Option Addendum
      1. 10.1.1 Packaging Information
      2. 10.1.2 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

3 Pin Configuration and Functions

TPS650860 pinout_fix.gif
The thermal pad must be connected to the system power ground plane.
Figure 3-1 RSK (VQFN) Pin Map Diagram

Pin Functions

NO. NAME I/O DESCRIPTION
SMPS REGULATORS
1 FBGND2 I Remote negative feedback sense for BUCK2 controller. Connect to negative terminal of output capacitor.
2 FBVOUT2 I Remote positive feedback sense for BUCK2 controller. Connect to positive terminal of output capacitor.
3 DRVH2 O High-side gate driver output for BUCK2 controller.
4 SW2 I Switch node connection for BUCK2 controller.
5 BOOT2 I Bootstrap pin for BUCK2 controller. Connect a 100-nF ceramic capacitor between this pin and SW2 pin.
6 PGNDSNS2 I Power GND connection for BUCK2. Connect to ground terminal of external low-side FET.
7 DRVL2 O Low-side gate driver output for BUCK2 controller.
8 DRV5V_2_A1 I 5-V supply to BUCK2 gate driver and LDOA1. Bypass to ground with a 2.2-µF (TYP) ceramic capacitor. Shorted on board to LDO5P0 pin typically.
10 LX3 O Switch node connection for BUCK3 converter.
11 PVIN3 I Power input to BUCK3 converter. Bypass to ground with a 10-µF (TYP) ceramic capacitor.
12 FB3 I Remote feedback sense for BUCK3 converter. Connect to positive terminal of output capacitor.
20 LX5 O Switch node connection for BUCK5 converter.
21 PVIN5 I Power input to BUCK5 converter. Bypass to ground with a 10-µF (TYP) ceramic capacitor.
22 FB5 I Remote feedback sense for BUCK5 converter. Connect to positive terminal of output capacitor.
23 FB4 I Remote feedback sense for BUCK4 converter. Connect to positive terminal of output capacitor.
24 PVIN4 I Power input to BUCK4 converter. Bypass to ground with a 10-µF (TYP) ceramic capacitor.
25 LX4 O Switch node connection for BUCK4 converter.
29 FBVOUT1 I Remote feedback sense for BUCK1 controller. Connect to positive terminal of output capacitor.
30 ILIM1 I Current limit set pin for BUCK1 controller. Fit a resistor from this pin to ground to set current limit of external low-side FET.
33 DRVH1 O High-side gate driver output for BUCK1 controller.
34 SW1 I Switch node connection for BUCK1 controller.
35 BOOT1 I Bootstrap pin for BUCK1 controller. Connect a 100-nF ceramic capacitor between this pin and SW1 pin.
36 PGNDSNS1 I Power GND connection for BUCK1. Connect to ground terminal of external low-side FET.
37 DRVL1 O Low-side gate driver output for BUCK1 controller.
38 DRV5V_1_6 I 5-V supply to BUCK1 and BUCK6 gate drivers. Bypass to ground with a 2.2-µF (TYP) ceramic capacitor. Shorted on board to LDO5P0 pin typically.
39 DRVL6 O Low-side gate driver output for BUCK6 controller.
40 PGNDSNS6 I Power GND connection for BUCK6. Connect to ground terminal of external low-side FET.
41 BOOT6 I Bootstrap pin for BUCK6 controller. Connect a 100-nF ceramic capacitor between this pin and SW6 pin.
42 SW6 I Switch node connection for BUCK6 controller.
SMPS REGULATORS (continued)
43 DRVH6 O High-side gate driver output for BUCK6 controller.
44 FBVOUT6 I Remote feedback sense for BUCK6 controller. Connect to positive terminal of output capacitor.
45 ILIM6 I Current limit set pin for BUCK6 controller. Fit a resistor from this pin to ground to set current limit of external low-side FET.
64 ILIM2 I Current limit set pin for BUCK2 controller. Fit a resistor from this pin to ground to set current limit of external low-side FET.
LDO and LOAD SWITCHES
9 LDOA1 O LDOA1 output. Bypass to ground with a 4.7-µF (TYP) ceramic capacitor. Leave floating when not in use.
17 SWB1 O Output of load switch B1. Bypass to ground with a 0.1-µF (TYP) ceramic capacitor. Leave floating when not in use.
18 PVINSWB1_B2 I Power supply to load switch B1 and B2. Bypass to ground with a 1-µF (TYP) ceramic capacitor to improve transient performance. Connect to ground when not in use.
19 SWB2 O Output of load switch B2. Bypass to ground with a 0.1-µF (TYP) ceramic capacitor. Leave floating when not in use.
31 SWA1 O Output of load switch A1. Bypass to ground with a 0.1-µF (TYP) ceramic capacitor. Leave floating when not in use.
32 PVINSWA1 I Power supply to load switch A1. Bypass to ground with a 1-µF (TYP) ceramic capacitor to improve transient performance. Connect to ground when not in use.
46 PVINVTT I Power supply to VTT LDO. Bypass to ground with a 10-µF (MIN) ceramic capacitor.
47 VTT O Output of load VTT LDO. Bypass to ground with 2× 22-µF (MIN) ceramic capacitors.
48 VTTFB I Remote feedback sense for VTT LDO. Connect to positive terminal of output capacitor.
49 LDOA3 O Output of LDOA3. Bypass to ground with a 4.7-µF (TYP) ceramic capacitor. Leave floating when not in use.
50 PVINLDOA2_A3 I Power supply to LDOA2 and LDOA3. Bypass to ground with a 4.7-µF (TYP) ceramic capacitor. Connect to ground when not in use.
51 LDOA2 O Output of LDOA2. Bypass to ground with a 4.7-µF (TYP) ceramic capacitor. Leave floating when not in use.
54 LDO3P3 O Output of 3.3-V internal LDO. Bypass to ground with a 4.7-µF (TYP) ceramic capacitor.
56 LDO5P0 O Output of 5-V internal LDO or an internal switch that connects this pin to V5ANA. Bypass to ground with a 4.7-µF (TYP) ceramic capacitor.
57 V5ANA I External 5-V supply input to internal load switch that connects this pin to LDO5P0 pin. Bypass this pin with an optional ceramic capacitor to improve transient performance.
INTERFACE
13 CTL1 I Active-high VR enable pin. A group of VRs can be assigned to be enabled at assertion or disabled at deassertion of this pin.
14 CTL6/SLPENB2 I Active-high VR enable pin. A group of VRs can be assigned to be enabled at assertion or disabled at deassertion of this pin. Alternatively, when configured to active-low sleep enable, a group of VRs chosen can be entered into (L) or out of (H) sleep state where their output voltages may be different from those in normal state.
15 IRQB O Open-drain output interrupt pin. Refer to Section 5.9.3 for definitions.
16 GPO1 O General purpose output that can be configured to either open-drain or push-pull arrangement. Regardless of the configuration, the pin can be programmed either to reflect power good status of VRs of any choice or to be controlled by an I2C register bit by the user, which then can be used as an enable signal to an external VR.
26 GPO2 O General purpose output that can be configured to either open-drain or push-pull arrangement. Regardless of the configuration, the pin can be programmed either to reflect power good status of VRs of any choice or to be controlled by an I2C register bit by the user, which then can be used as an enable signal to an external VR.
27 GPO3 O General purpose output that can be configured to either open-drain or push-pull arrangement. Regardless of the configuration, the pin can be programmed either to reflect power good status of VRs of any choice or to be controlled by an I2C register bit by the user, which then can be used as an enable signal to an external VR.
28 GPO4 O Open-drain output that can be configured to reflect power good status of VRs of any choice or to be controlled by an I2C register bit by the user, which then can be used as an enable signal to an external VR.
58 CLK I I2C clock
59 DATA I/O I2C data
60 CTL2 I Active-high VR enable pin. A group of VRs can be assigned to be enabled at assertion or disabled at deassertion of this pin.
61 CTL3/SLPENB1 I Active-high VR enable pin. A group of VRs can be assigned to be enabled at assertion or disabled at deassertion of this pin. Alternatively, when configured to active-low sleep enable, a group of VRs chosen can be entered into (L) or out of (H) sleep state where their output voltages may be different from those in normal state.
62 CTL4 I Active-high VR enable pin. A group of VRs can be assigned to be enabled at assertion or disabled at deassertion of this pin.
63 CTL5 I Active-high VR enable pin. A group of VRs can be assigned to be enabled at assertion or disabled at deassertion of this pin.
REFERENCE
53 VREF O Band-gap reference output. Stabilize it by connecting a 100-nF (TYP) ceramic capacitor between this pin and quiet ground.
52 AGND — Analog ground. Do not connect to the thermal pad ground on top layer. Connect to ground of VREF capacitor.
55 VSYS I System voltage detection and input to internal LDOs (3.3 V and 5 V). Bypass to ground with a 1-µF (TYP) ceramic capacitor.
THERMAL PAD
Thermal pad — Connect to PCB ground plane using multiple vias for good thermal and electrical performance.