JAJSFU4 July 2018 TPS650861
PRODUCTION DATA.
This section describes the registers that can be accessed using I2C address 0x38. These registers can only be accessed by putting the device into programming mode. See the TPS65086100 OTP Memory Programming Guide for more information on putting the device into programming mode. It is recommended to use the OTP generator tool to make changes to these OTP settings. Do not attempt to write a RESERVED R/W bit to the opposite value. When the reset value of a bit register is 0bX, it means the bit value is coming from the OTP memory.
NOTE
There are additional registers not shown that are set by the OTP generator tool.
Address | Name | Short Description |
---|---|---|
02h | OTP_CTRL1 | OTP control register for programming. |
03h | OTP_CTRL2 | OTP control register for selecting OTP bank. |
07h | BUCK1_CTRL_EN1 | BUCK1 enable control register 1. |
08h | BUCK1_CTRL_EN2 | BUCK1 enable control register 2. |
09h | BUCK1_CTRL_EN3 | BUCK1 enable control register 3. |
0Ah | BUCK2_CTRL_EN1 | BUCK2 enable control register 1. |
0Bh | BUCK2_CTRL_EN2 | BUCK2 enable control register 2. |
0Ch | BUCK2_CTRL_EN3 | BUCK2 enable control register 3. |
0Dh | BUCK3_CTRL_EN1 | BUCK3 enable control register 1. |
0Eh | BUCK3_CTRL_EN2 | BUCK3 enable control register 2. |
0Fh | BUCK3_CTRL_EN3 | BUCK3 enable control register 3. |
10h | BUCK4_CTRL_EN1 | BUCK4 enable control register 1. |
11h | BUCK4_CTRL_EN2 | BUCK4 enable control register 2. |
12h | BUCK4_CTRL_EN3 | BUCK4 enable control register 3. |
13h | BUCK5_CTRL_EN1 | BUCK5 enable control register 1. |
14h | BUCK5_CTRL_EN2 | BUCK5 enable control register 2. |
15h | BUCK5_CTRL_EN3 | BUCK5 enable control register 3. |
16h | BUCK6_CTRL_EN1 | BUCK6 enable control register 1. |
17h | BUCK6_CTRL_EN2 | BUCK6 enable control register 2. |
18h | BUCK6_CTRL_EN3 | BUCK6 enable control register 3. |
19h | SWA1_CTRL_EN1 | SWA1 enable control register 1. |
1Ah | SWA1_CTRL_EN2 | SWA1 enable control register 2. |
1Bh | SWA1_CTRL_EN3 | SWA1 enable control register 3. |
1Ch | LDOA2_CTRL_EN1 | LDOA2 enable control register 1. |
1Dh | LDOA2_CTRL_EN2 | LDOA2 enable control register 2. |
1Eh | LDOA2_CTRL_EN3 | LDOA2 enable control register 3. |
1Fh | LDOA3_CTRL_EN1 | LDOA3 enable control register 1. |
20h | LDOA3_CTRL_EN2 | LDOA3 enable control register 2. |
21h | LDOA3_CTRL_EN3 | LDOA3 enable control register 3. |
22h | SWB1_CTRL_EN1 | SWB1 enable control register 1. |
23h | SWB1_CTRL_EN2 | SWB1 enable control register 2. |
24h | SWB1_CTRL_EN3 | SWB1 enable control register 3. |
25h | SWB2_LDOA1_CTRL_EN1 | SWB2 or LDOA1 enable control register 1. |
26h | SWB2_LDOA1_CTRL_EN2 | SWB2 or LDOA1 enable control register 2. |
27h | SWB2_LDOA1_CTRL_EN3 | SWB2 or LDOA1 enable control register 3. |
29h | SLP_PIN | Sleep pin select for BUCK1-6, LDOA2, and LDOA3. |
2Ah | OUTPUT_MODE | GPO output mode control. |
5Fh | I2C_SLAVE_ADDR | I2C address control |