JAJSFU4 July 2018 TPS650861
PRODUCTION DATA.
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|
Bit Name | RESERVED | RESERVED | BUCK3
_MODE |
BUCK2
_MODE |
BUCK1
_MODE |
BUCK3
_DIS |
BUCK2
_DIS |
BUCK1
_DIS |
TPS65086100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Access | R | R | R/W | R/W | R/W | R/W | R/W | R/W |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
5 | BUCK3_MODE | R/W | X | This field sets the BUCK3 regulator operating mode.
0: Reserved 1: Forced PWM mode |
4 | BUCK2_MODE | R/W | X | This field sets the BUCK2 regulator operating mode.
0: Automatic mode 1: Forced PWM mode |
3 | BUCK1_MODE | R/W | X | This field sets the BUCK1 regulator operating mode.
0: Automatic mode 1: Forced PWM mode |
2 | BUCK3_DIS | R/W | X | BUCK3 Disable Bit. Writing 0 to this bit forces BUCK3 to turn off regardless of any control input pin (CTL1–CTL6) status.
0: Disable 1: Enable |
1 | BUCK2_DIS | R/W | X | BUCK2 Disable Bit. Writing 0 to this bit forces BUCK2 to turn off regardless of any control input pin (CTL1–CTL6) status.
0: Disable 1: Enable |
0 | BUCK1_DIS | R/W | X | BUCK1 Disable Bit. Writing 0 to this bit forces BUCK1 to turn off regardless of any control input pin (CTL1–CTL6) status.
0: Disable 1: Enable |