JAJSE17 October   2017 TPS6508700

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 機能ブロック図
  2. 2改訂履歴
  3. 3Pin Configuration and Functions
    1. 3.1 Pin Functions
  4. 4Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  Thermal Information
    5. 4.5  Electrical Characteristics: Total Current Consumption
    6. 4.6  Electrical Characteristics: Reference and Monitoring System
    7. 4.7  Electrical Characteristics: Buck Controllers
    8. 4.8  Electrical Characteristics: Synchronous Buck Converters
    9. 4.9  Electrical Characteristics: LDOs
    10. 4.10 Electrical Characteristics: Load Switches
    11. 4.11 Digital Signals: I2C Interface
    12. 4.12 Digital Input Signals (CTLx)
    13. 4.13 Digital Output Signals (IRQB, GPOx)
    14. 4.14 Timing Requirements
    15. 4.15 Switching Characteristics
    16. 4.16 Typical Characteristics
  5. 5Detailed Description
    1. 5.1 Overview
    2. 5.2 Functional Block Diagram
    3. 5.3 SMPS Voltage Regulators
      1. 5.3.1 Controller Overview
      2. 5.3.2 Converter Overview
      3. 5.3.3 Dynamic Voltage Scaling
      4. 5.3.4 Current Limit
    4. 5.4 LDO Regulators and Load Switches
      1. 5.4.1 VTT LDO
      2. 5.4.2 LDOA1-LDOA3
      3. 5.4.3 Load Switches
    5. 5.5 Power Good Information (PGOOD or PG) and GPO Pins
    6. 5.6 Power Sequencing and Voltage-Rail Control
      1. 5.6.1 Power-Up and Power-Down Sequencing
      2. 5.6.2 Emergency Shutdown
    7. 5.7 Device Functional Modes
      1. 5.7.1 Off Mode
      2. 5.7.2 Standby Mode
      3. 5.7.3 Active Mode
    8. 5.8 I2C Interface
      1. 5.8.1 F/S-Mode Protocol
    9. 5.9 Register Maps
      1. 5.9.1  Register Map Summary
      2. 5.9.2  DEVICEID: PMIC Device and Revision ID Register (offset = 1h) [reset = 10h]
      3. 5.9.3  IRQ: PMIC Interrupt Register (offset = 2h) [reset = 0h]
      4. 5.9.4  IRQ_MASK: PMIC Interrupt Mask Register (offset = 3h) [reset = FFh]
      5. 5.9.5  PMICSTAT: PMIC Status Register (offset = 4h) [reset = 0h]
      6. 5.9.6  SHUTDNSRC: PMIC Shut-Down Event Register (offset = 5h) [reset = 0h]
      7. 5.9.7  BUCK2CTRL: BUCK2 Control Register (offset = 21h) [reset = 50h]
      8. 5.9.8  BUCK3DECAY: BUCK3 Decay Control Register (offset = 22h) [reset = 70h]
      9. 5.9.9  BUCK3VID: BUCK3 VID Register (offset = 23h) [reset = 70h]
      10. 5.9.10 BUCK3SLPCTRL: BUCK3 Sleep Control VID Register (offset = 24h) [reset = 70h]
      11. 5.9.11 BUCK4CTRL: BUCK4 Control Register (offset = 25h) [reset = Dh]
      12. 5.9.12 BUCK5CTRL: BUCK5 Control Register (offset = 26h) [reset = Dh]
      13. 5.9.13 BUCK6CTRL: BUCK6 Control Register (offset = 27h) [reset = Dh]
      14. 5.9.14 LDOA2CTRL: LDOA2 Control Register (offset = 28h) [reset = Ch]
      15. 5.9.15 LDOA3CTRL: LDOA3 Control Register (offset = 29h) [reset = 3Ch]
      16. 5.9.16 DISCHCTRL1: Discharge Control1 Register (offset = 40h) [reset = 55h]
      17. 5.9.17 DISCHCTRL2: Discharge Control2 Register (offset = 41h) [reset = 55h]
      18. 5.9.18 DISCHCTRL3: Discharge Control3 Register (offset = 42h) [reset = 15h]
      19. 5.9.19 PG_DELAY1: Power Good Delay1 Register (offset = 43h) [reset = 0h]
      20. 5.9.20 FORCESHUTDN: Force Emergency Shutdown Control Register (offset = 91h) [reset = 0h]
      21. 5.9.21 BUCK2SLPCTRL: BUCK2 Sleep Control Register (offset = 93h) [reset = 50h]
      22. 5.9.22 BUCK4VID: BUCK4 VID Register (offset = 94h) [reset = 20h]
      23. 5.9.23 BUCK4SLPVID: BUCK4 Sleep VID Register (offset = 95h) [reset = 20h]
      24. 5.9.24 BUCK5VID: BUCK5 VID Register (offset = 96h) [reset = 70h]
      25. 5.9.25 BUCK5SLPVID: BUCK5 Sleep VID Register (offset = 97h) [reset = E8h]
      26. 5.9.26 BUCK6VID: BUCK6 VID Register (offset = 98h) [reset = E8h]
      27. 5.9.27 BUCK6SLPVID: BUCK6 Sleep VID Register (offset = 99h) [reset = E8h]
      28. 5.9.28 LDOA2VID: LDOA2 VID Register (offset = 9Ah) [reset = FFh]
      29. 5.9.29 LDOA3VID: LDOA3 VID Register (offset = 9Bh) [reset = AAh]
      30. 5.9.30 BUCK123CTRL: BUCK1-3 Control Register (offset = 9Ch) [reset = 7h]
      31. 5.9.31 PG_DELAY2: Power Good Delay2 Register (offset = 9Dh) [reset = 21h]
      32. 5.9.32 SWVTT_DIS: SWVTT Disable Register (offset = 9Fh) [reset = 0h]
      33. 5.9.33 I2C_RAIL_EN1: VR Pin Enable Override1 Register (offset = A0h) [reset = 80h]
      34. 5.9.34 I2C_RAIL_EN2/GPOCTRL: VR Pin Enable Override2/GPO Control Register (offset = A1h) [reset = 89h]
      35. 5.9.35 PWR_FAULT_MASK1: VR Power Fault Mask1 Register (offset = A2h) [reset = C0h]
      36. 5.9.36 PWR_FAULT_MASK2: VR Power Fault Mask2 Register (offset = A3h) [reset = 3Fh]
      37. 5.9.37 GPO1PG_CTRL1: GPO1 PG Control1 Register (offset = A4h) [reset = C2h]
      38. 5.9.38 GPO1PG_CTRL2: GPO1 PG Control2 Register (offset = A5h) [reset = AFh]
      39. 5.9.39 GPO4PG_CTRL1: GPO4 PG Control1 Register (offset = A6h) [reset = 0h]
      40. 5.9.40 GPO4PG_CTRL2: GPO4 PG Control2 Register (offset = A7h) [reset = 0h]
      41. 5.9.41 GPO2PG_CTRL1: GPO2 PG Control1 Register (offset = A8h) [reset = C0h]
      42. 5.9.42 GPO2PG_CTRL2: GPO2 PG Control2 Register (offset = A9h) [reset = 2Fh]
      43. 5.9.43 GPO3PG_CTRL1: GPO3 PG Control1 Register (offset = AAh) [reset = 0h]
      44. 5.9.44 GPO3PG_CTRL2: GPO3 PG Control2 Register (offset = ABh) [reset = 0h]
      45. 5.9.45 MISCSYSPG Register (offset = ACh) [reset = FFh]
      46. 5.9.46 LDOA1CTRL: LDOA1 Control Register (offset = AEh) [reset = 7Dh]
      47. 5.9.47 PG_STATUS1: Power Good Status1 Register (offset = B0h) [reset = 0h]
      48. 5.9.48 PG_STATUS2: Power Good Status2 Register (offset = B1h) [reset = 0h]
      49. 5.9.49 PWR_FAULT_STATUS1: Power Fault Status1 Register (offset = B2h) [reset = 0h]
      50. 5.9.50 PWR_FAULT_STATUS2: Power Fault Status2 Register (offset = B3h) [reset = 0h]
      51. 5.9.51 TEMPCRIT: Temperature Fault Status Register (offset = B4h) [reset = 0h]
      52. 5.9.52 TEMPHOT: Temperature Hot Status Register (offset = B5h) [reset = 0h]
      53. 5.9.53 OC_STATUS: Overcurrent Fault Status Register (offset = B6h) [reset = 0h]
  6. 6Applications, Implementation, and Layout
    1. 6.1 Application Information
    2. 6.2 Typical Application
      1. 6.2.1 Design Requirements
      2. 6.2.2 Detailed Design Procedure
        1. 6.2.2.1 Controller Design Procedure
          1. 6.2.2.1.1 Controller With External Feedback Resistor
          2. 6.2.2.1.2 Selecting the Inductor
          3. 6.2.2.1.3 Selecting the Output Capacitors
          4. 6.2.2.1.4 Selecting the FETs
          5. 6.2.2.1.5 Bootstrap Capacitor
          6. 6.2.2.1.6 Setting the Current Limit
          7. 6.2.2.1.7 Selecting the Input Capacitors
        2. 6.2.2.2 Converter Design Procedure
          1. 6.2.2.2.1 Selecting the Inductor
          2. 6.2.2.2.2 Selecting the Output Capacitors
          3. 6.2.2.2.3 Selecting the Input Capacitors
        3. 6.2.2.3 LDO Design Procedure
      3. 6.2.3 Application Curves
      4. 6.2.4 Layout
        1. 6.2.4.1 Layout Guidelines
        2. 6.2.4.2 Layout Example
    3. 6.3 Power Supply Coupling and Bulk Capacitors
    4. 6.4 Do's and Don'ts
  7. 7デバイスおよびドキュメントのサポート
    1. 7.1 デバイス・サポート
      1. 7.1.1 Third-Party Products Disclaimer
    2. 7.2 ドキュメントのサポート
      1. 7.2.1 関連資料
    3. 7.3 ドキュメントの更新通知を受け取る方法
    4. 7.4 Community Resources
    5. 7.5 商標
    6. 7.6 静電気放電に関する注意事項
    7. 7.7 Glossary
  8. 8メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RSK|64
サーマルパッド・メカニカル・データ
発注情報

3 Pin Configuration and Functions

Figure 3-1 shows the 64-pin RSK plastic quad-flatpack no-lead package with exposed thermal pad.

The thermal pad must be connected to the system power ground plane.
Figure 3-1 64-pin RSK VQFN (Top View)

3.1 Pin Functions

Pin Functions

PIN I/O DESCRIPTION
NO. NAME
SMPS REGULATORS
1 FBGND2 I Remote negative feedback sense for BUCK2 controller. Connect to negative terminal of output capacitor or input capacitor of load.
2 FBVOUT2 I Remote positive feedback sense for BUCK2 controller. Connect to positive terminal of output capacitor or input capacitor of load.
3 DRVH2 O High-side gate driver output for BUCK2 controller.
4 SW2 I Switch node connection for BUCK2 controller.
5 BOOT2 I Bootstrap pin for BUCK2 controller. Connect a 100-nF ceramic capacitor between this pin and SW2 pin.
6 PGNDSNS2 I Power GND sense connection for BUCK2. Connect to ground terminal of external low-side FET.
7 DRVL2 O Low-side gate driver output for BUCK2 controller.
8 DRV5V_2_A1 I 5-V supply to BUCK2 gate driver and LDOA1. Bypass to ground with a 2.2-µF (typical) ceramic capacitor. Shorted on board to LDO5P0 pin.
10 LX3 O Switch node connection for BUCK3 converter.
11 PVIN3 I Power input to BUCK3 converter. Bypass to ground with a 10-µF (typical) ceramic capacitor.
12 FB3 I Remote feedback sense for BUCK3 converter. Connect to positive terminal of output capacitor.
20 LX5 O Switch node connection for BUCK5 converter.
21 PVIN5 I Power input to BUCK5 converter. Bypass to ground with a 10-µF (typical) ceramic capacitor.
22 FB5 I Remote feedback sense for BUCK5 converter. Connect to positive terminal of output capacitor.
23 FB4 I Remote feedback sense for BUCK4 converter. Connect to positive terminal of output capacitor.
24 PVIN4 I Power input to BUCK4 converter. Bypass to ground with a 10-µF (typical) ceramic capacitor.
25 LX4 O Switch node connection for BUCK4 converter.
29 FBVOUT1 I Remote feedback sense for BUCK1 controller. Connect to external feedback near either output capacitor or input capacitor of load. Recommend a 4.7-pF feedforward capacitor.
30 ILIM1 I Current limit set pin for BUCK1 controller. Fit a resistor from this pin to ground to set current limit of external low-side FET.
33 DRVH1 O High-side gate driver output for BUCK1 controller.
34 SW1 I Switch node connection for BUCK1 controller.
35 BOOT1 I Bootstrap pin for BUCK1 controller. Connect a 100-nF ceramic capacitor between this pin and SW1 pin.
36 PGNDSNS1 I Power GND sense connection for BUCK1. Connect to ground terminal of external low-side FET.
37 DRVL1 O Low-side gate driver output for BUCK1 controller.
38 DRV5V_1_6 I 5-V supply to BUCK1 and BUCK6 gate drivers. Bypass to ground with a 2.2-µF (typical) ceramic capacitor. Shorted on board to LDO5P0 pin.
39 DRVL6 O Low-side gate driver output for BUCK6 controller.
40 PGNDSNS6 I Power GND sense connection for BUCK6. Connect to ground terminal of external low-side FET.
41 BOOT6 I Bootstrap pin for BUCK6 controller. Connect a 100-nF ceramic capacitor between this pin and SW6 pin.
42 SW6 I Switch node connection for BUCK6 controller.
43 DRVH6 O High-side gate driver output for BUCK6 controller.
44 FBVOUT6 I Remote feedback sense for BUCK6 controller. Connect to positive terminal of output capacitor or input capacitor of load.
45 ILIM6 I Current limit set pin for BUCK6 controller. Fit a resistor from this pin to ground to set current limit of external low-side FET.
64 ILIM2 I Current limit set pin for BUCK2 controller. Fit a resistor from this pin to ground to set current limit of external low-side FET.
LDO AND LOAD SWITCHES
9 LDOA1 O LDOA1 output. Bypass to ground with a 4.7-µF (typical) ceramic capacitor.
17 SWB1 O Output of load switch B1. Bypass to ground with a 0.1-µF (typical) ceramic capacitor. Leave floating when not in use.
18 PVINSWB1_B2 I Power supply to load switch B1 and B2. Bypass to ground with a 1-µF (typical) ceramic capacitor to improve transient performance. Connect to ground when not in use.
19 SWB2 O Output of load switch B2. Bypass to ground with a 0.1-µF (typical) ceramic capacitor. Leave floating when not in use.
31 SWA1 O Output of load switch A1. Bypass to ground with a 0.1-µF (typical) ceramic capacitor. Leave floating when not in use.
32 PVINSWA1 I Power supply to load switch A1. Bypass to ground with a 1-µF (typical) ceramic capacitor to improve transient performance. Connect to ground when not in use.
46 PVINVTT I Power supply to VTT LDO. Bypass to ground with a 10-µF (minimum) ceramic capacitor. Connect to ground when not in use.
47 VTT O Output of load VTT LDO. Bypass to ground with 2× 22-µF (minimum) ceramic capacitors. Leave floating when not in use.
48 VTTFB I Remote feedback sense for VTT LDO. Connect to positive terminal of output capacitor. Leave floating when not in use.
49 LDOA3 O Output of LDOA3. Bypass to ground with a 4.7-µF (typical) ceramic capacitor. Leave floating when not in use.
50 PVINLDOA2_A3 I Power supply to LDOA2 and LDOA3. Bypass to ground with a 4.7-µF (typical) ceramic capacitor. Connect to ground when not in use.
51 LDOA2 O Output of LDOA2. Bypass to ground with a 4.7-µF (typical) ceramic capacitor. Leave floating when not in use.
54 LDO3P3 O Output of 3.3-V internal LDO. Bypass to ground with a 4.7-µF (typical) ceramic capacitor.
56 LDO5P0 O Output of 5-V internal LDO or an internal switch that connects this pin to V5ANA. Bypass to ground with a 4.7-µF (typical) ceramic capacitor.
57 V5ANA I External 5-V supply input to internal load switch that connects this pin to LDO5P0 pin. Bypass this pin with an optional ceramic capacitor to improve transient performance.
INTERFACE
13 CTL1 I Active-high enable pin for BUCK4, BUCK5, and BUCK6. Connect to AND of GPIO_G3 and EN_S5 for typical sequencing.
14 CTL6/SLPENB2 I Active-high unused control signal. Sleep state control for BUCK6 (masked).
15 IRQB O Open-drain output interrupt pin. Refer to Section 5.9.3 for definitions.
16 GPO1 O PG_S5 output indicates S5 power state has been reached. Open drain output, pull up to appropriate voltage rail.
26 GPO2 O PG_S0 output indicates S0 power state has been reached. Open drain output, pull up to appropriate voltage rail.
27 GPO3 O General purpose output that is configured to push-pull output at 3.3V and controlled by I2C. Default state is low.
28 GPO4 O General purpose output that is configured to open-drain output and controlled by I2C. Default state is high.
58 CLK I I2C clock
59 DATA I/O I2C data
60 CTL2 I Active-high LDOA2 and LDOA3 enable. Tie to GND unless using this pin to disable LDOA2 and LDOA3 after enabling them by I2C.
61 CTL3/SLPENB1 I Active-high VTT LDO enable and sleep state control for BUCK1-BUCK5 (masked), LDOA2, and LDOA3.
62 CTL4 I Active-high enable pin for BUCK1 and BUCK3. Connect to OR of CTL1 input and inverted GPIO_G3 for typical sequencing. SWA1, SWB1, and SWB2 can also use CTL4 if configured by I2C after boot.
63 CTL5 I Active-high enable pin for BUCK2. Connect to EN_S0 for typical sequencing.
REFERENCE
53 VREF O Band-gap reference output. Stabilize it by connecting a 100-nF (typical) ceramic capacitor between this pin and quiet ground.
52 AGND — Analog ground. Do not connect to the thermal pad ground on top layer. Connect to ground of VREF capacitor.
55 VSYS I System voltage detection and input to internal LDOs (3.3 V and 5 V). Bypass to ground with a 1-µF (typical) ceramic capacitor.
THERMAL PAD
— Thermal pad — Connect to PCB ground plane using multiple vias for good thermal and electrical performance.