JAJSE17 October   2017 TPS6508700

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 機能ブロック図
  2. 2改訂履歴
  3. 3Pin Configuration and Functions
    1. 3.1 Pin Functions
  4. 4Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  Thermal Information
    5. 4.5  Electrical Characteristics: Total Current Consumption
    6. 4.6  Electrical Characteristics: Reference and Monitoring System
    7. 4.7  Electrical Characteristics: Buck Controllers
    8. 4.8  Electrical Characteristics: Synchronous Buck Converters
    9. 4.9  Electrical Characteristics: LDOs
    10. 4.10 Electrical Characteristics: Load Switches
    11. 4.11 Digital Signals: I2C Interface
    12. 4.12 Digital Input Signals (CTLx)
    13. 4.13 Digital Output Signals (IRQB, GPOx)
    14. 4.14 Timing Requirements
    15. 4.15 Switching Characteristics
    16. 4.16 Typical Characteristics
  5. 5Detailed Description
    1. 5.1 Overview
    2. 5.2 Functional Block Diagram
    3. 5.3 SMPS Voltage Regulators
      1. 5.3.1 Controller Overview
      2. 5.3.2 Converter Overview
      3. 5.3.3 Dynamic Voltage Scaling
      4. 5.3.4 Current Limit
    4. 5.4 LDO Regulators and Load Switches
      1. 5.4.1 VTT LDO
      2. 5.4.2 LDOA1-LDOA3
      3. 5.4.3 Load Switches
    5. 5.5 Power Good Information (PGOOD or PG) and GPO Pins
    6. 5.6 Power Sequencing and Voltage-Rail Control
      1. 5.6.1 Power-Up and Power-Down Sequencing
      2. 5.6.2 Emergency Shutdown
    7. 5.7 Device Functional Modes
      1. 5.7.1 Off Mode
      2. 5.7.2 Standby Mode
      3. 5.7.3 Active Mode
    8. 5.8 I2C Interface
      1. 5.8.1 F/S-Mode Protocol
    9. 5.9 Register Maps
      1. 5.9.1  Register Map Summary
      2. 5.9.2  DEVICEID: PMIC Device and Revision ID Register (offset = 1h) [reset = 10h]
      3. 5.9.3  IRQ: PMIC Interrupt Register (offset = 2h) [reset = 0h]
      4. 5.9.4  IRQ_MASK: PMIC Interrupt Mask Register (offset = 3h) [reset = FFh]
      5. 5.9.5  PMICSTAT: PMIC Status Register (offset = 4h) [reset = 0h]
      6. 5.9.6  SHUTDNSRC: PMIC Shut-Down Event Register (offset = 5h) [reset = 0h]
      7. 5.9.7  BUCK2CTRL: BUCK2 Control Register (offset = 21h) [reset = 50h]
      8. 5.9.8  BUCK3DECAY: BUCK3 Decay Control Register (offset = 22h) [reset = 70h]
      9. 5.9.9  BUCK3VID: BUCK3 VID Register (offset = 23h) [reset = 70h]
      10. 5.9.10 BUCK3SLPCTRL: BUCK3 Sleep Control VID Register (offset = 24h) [reset = 70h]
      11. 5.9.11 BUCK4CTRL: BUCK4 Control Register (offset = 25h) [reset = Dh]
      12. 5.9.12 BUCK5CTRL: BUCK5 Control Register (offset = 26h) [reset = Dh]
      13. 5.9.13 BUCK6CTRL: BUCK6 Control Register (offset = 27h) [reset = Dh]
      14. 5.9.14 LDOA2CTRL: LDOA2 Control Register (offset = 28h) [reset = Ch]
      15. 5.9.15 LDOA3CTRL: LDOA3 Control Register (offset = 29h) [reset = 3Ch]
      16. 5.9.16 DISCHCTRL1: Discharge Control1 Register (offset = 40h) [reset = 55h]
      17. 5.9.17 DISCHCTRL2: Discharge Control2 Register (offset = 41h) [reset = 55h]
      18. 5.9.18 DISCHCTRL3: Discharge Control3 Register (offset = 42h) [reset = 15h]
      19. 5.9.19 PG_DELAY1: Power Good Delay1 Register (offset = 43h) [reset = 0h]
      20. 5.9.20 FORCESHUTDN: Force Emergency Shutdown Control Register (offset = 91h) [reset = 0h]
      21. 5.9.21 BUCK2SLPCTRL: BUCK2 Sleep Control Register (offset = 93h) [reset = 50h]
      22. 5.9.22 BUCK4VID: BUCK4 VID Register (offset = 94h) [reset = 20h]
      23. 5.9.23 BUCK4SLPVID: BUCK4 Sleep VID Register (offset = 95h) [reset = 20h]
      24. 5.9.24 BUCK5VID: BUCK5 VID Register (offset = 96h) [reset = 70h]
      25. 5.9.25 BUCK5SLPVID: BUCK5 Sleep VID Register (offset = 97h) [reset = E8h]
      26. 5.9.26 BUCK6VID: BUCK6 VID Register (offset = 98h) [reset = E8h]
      27. 5.9.27 BUCK6SLPVID: BUCK6 Sleep VID Register (offset = 99h) [reset = E8h]
      28. 5.9.28 LDOA2VID: LDOA2 VID Register (offset = 9Ah) [reset = FFh]
      29. 5.9.29 LDOA3VID: LDOA3 VID Register (offset = 9Bh) [reset = AAh]
      30. 5.9.30 BUCK123CTRL: BUCK1-3 Control Register (offset = 9Ch) [reset = 7h]
      31. 5.9.31 PG_DELAY2: Power Good Delay2 Register (offset = 9Dh) [reset = 21h]
      32. 5.9.32 SWVTT_DIS: SWVTT Disable Register (offset = 9Fh) [reset = 0h]
      33. 5.9.33 I2C_RAIL_EN1: VR Pin Enable Override1 Register (offset = A0h) [reset = 80h]
      34. 5.9.34 I2C_RAIL_EN2/GPOCTRL: VR Pin Enable Override2/GPO Control Register (offset = A1h) [reset = 89h]
      35. 5.9.35 PWR_FAULT_MASK1: VR Power Fault Mask1 Register (offset = A2h) [reset = C0h]
      36. 5.9.36 PWR_FAULT_MASK2: VR Power Fault Mask2 Register (offset = A3h) [reset = 3Fh]
      37. 5.9.37 GPO1PG_CTRL1: GPO1 PG Control1 Register (offset = A4h) [reset = C2h]
      38. 5.9.38 GPO1PG_CTRL2: GPO1 PG Control2 Register (offset = A5h) [reset = AFh]
      39. 5.9.39 GPO4PG_CTRL1: GPO4 PG Control1 Register (offset = A6h) [reset = 0h]
      40. 5.9.40 GPO4PG_CTRL2: GPO4 PG Control2 Register (offset = A7h) [reset = 0h]
      41. 5.9.41 GPO2PG_CTRL1: GPO2 PG Control1 Register (offset = A8h) [reset = C0h]
      42. 5.9.42 GPO2PG_CTRL2: GPO2 PG Control2 Register (offset = A9h) [reset = 2Fh]
      43. 5.9.43 GPO3PG_CTRL1: GPO3 PG Control1 Register (offset = AAh) [reset = 0h]
      44. 5.9.44 GPO3PG_CTRL2: GPO3 PG Control2 Register (offset = ABh) [reset = 0h]
      45. 5.9.45 MISCSYSPG Register (offset = ACh) [reset = FFh]
      46. 5.9.46 LDOA1CTRL: LDOA1 Control Register (offset = AEh) [reset = 7Dh]
      47. 5.9.47 PG_STATUS1: Power Good Status1 Register (offset = B0h) [reset = 0h]
      48. 5.9.48 PG_STATUS2: Power Good Status2 Register (offset = B1h) [reset = 0h]
      49. 5.9.49 PWR_FAULT_STATUS1: Power Fault Status1 Register (offset = B2h) [reset = 0h]
      50. 5.9.50 PWR_FAULT_STATUS2: Power Fault Status2 Register (offset = B3h) [reset = 0h]
      51. 5.9.51 TEMPCRIT: Temperature Fault Status Register (offset = B4h) [reset = 0h]
      52. 5.9.52 TEMPHOT: Temperature Hot Status Register (offset = B5h) [reset = 0h]
      53. 5.9.53 OC_STATUS: Overcurrent Fault Status Register (offset = B6h) [reset = 0h]
  6. 6Applications, Implementation, and Layout
    1. 6.1 Application Information
    2. 6.2 Typical Application
      1. 6.2.1 Design Requirements
      2. 6.2.2 Detailed Design Procedure
        1. 6.2.2.1 Controller Design Procedure
          1. 6.2.2.1.1 Controller With External Feedback Resistor
          2. 6.2.2.1.2 Selecting the Inductor
          3. 6.2.2.1.3 Selecting the Output Capacitors
          4. 6.2.2.1.4 Selecting the FETs
          5. 6.2.2.1.5 Bootstrap Capacitor
          6. 6.2.2.1.6 Setting the Current Limit
          7. 6.2.2.1.7 Selecting the Input Capacitors
        2. 6.2.2.2 Converter Design Procedure
          1. 6.2.2.2.1 Selecting the Inductor
          2. 6.2.2.2.2 Selecting the Output Capacitors
          3. 6.2.2.2.3 Selecting the Input Capacitors
        3. 6.2.2.3 LDO Design Procedure
      3. 6.2.3 Application Curves
      4. 6.2.4 Layout
        1. 6.2.4.1 Layout Guidelines
        2. 6.2.4.2 Layout Example
    3. 6.3 Power Supply Coupling and Bulk Capacitors
    4. 6.4 Do's and Don'ts
  7. 7デバイスおよびドキュメントのサポート
    1. 7.1 デバイス・サポート
      1. 7.1.1 Third-Party Products Disclaimer
    2. 7.2 ドキュメントのサポート
      1. 7.2.1 関連資料
    3. 7.3 ドキュメントの更新通知を受け取る方法
    4. 7.4 Community Resources
    5. 7.5 商標
    6. 7.6 静電気放電に関する注意事項
    7. 7.7 Glossary
  8. 8メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RSK|64
サーマルパッド・メカニカル・データ
発注情報

4 Specifications

4.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
ANALOG
Input voltage from battery, VSYS –0.3 28 V
PVIN3, PVIN4, PVIN5, LDO5P0, DRV5V_1_6, DRV5V_2_A1, DRVL1, DRVL2, DRVL6 –0.3 7 V
V5ANA –0.3 6 V
PGNDSNS1, PGNDSNS2, PGNDSNS6, AGND, FBGND2 –0.3 0.3 V
DRVH1, DRVH2, DRVH6, BOOT1, BOOT2, BOOT6 –0.3 34 V
SW1, SW2, SW6, transient for less than 5 ns. –5 28 V
LX3, LX4, LX5 -0.3 7 V
LX3, LX4, LX5, transient for less than 20 ns. –2 9 V
Differential voltage, BOOTx to SWx –0.3 5.5 V
VREF, LDO3P3, FBVOUT1, FBVOUT2, FBVOUT6, FB3, FB4, FB5, ILIM1, ILIM2, ILIM6, PVINVTT, VTT, VTTFB, PVINSWA1, SWA1, PVINSWB1_B2, SWB1, SWB2, LDOA1 –0.3 3.6 V
PVINLDOA2_A3, LDOA2, LDOA3 –0.3 3.3 V
DIGITAL IO
DATA, CLK, GPO1-GPO3 –0.3 3.6 V
CTL1-CTL6, GPO4, IRQB –0.3 7 V
CHIP
Storage temperature, Tstg –40 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

4.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±250
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

4.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
ANALOG
VSYS 5.6 13 21 V
VREF –0.3 1.3 V
PVIN3, PVIN4, PVIN5, LDO5P0, V5ANA, DRV5V_1_6, DRV5V_2_A1 –0.3 5 5.5 V
PGNDSNS1, PGNDSNS2, PGNDSNS6, AGND, FBGND2 –0.3 0.3 V
DRVH1, DRVH2, DRVH6, BOOT1, BOOT2, BOOT6 –0.3 26.5 v
DRVL1, DRVL2, DRVL6 –0.3 5.5 V
SW1, SW2, SW6 –1 21 V
LX3, LX4, LX5 –1 5.5 V
FBVOUT1, FBVOUT2, FBVOUT6, FB3, FB4, FB5 –0.3 3.6 V
LDO3P3, ILIM1, ILIM2, ILIM6, LDOA1 –0.3 3.3 V
PVINVTT –0.3 FBVOUT6 V
VTT, VTTFB –0.3 FBVOUT6 / 2 V
PVINSWA1, SWA1 –0.3 3.3 3.6 V
PVINSWB1_B2, PVINLDOA2_A3, SWB1, SWB2 –0.3 1.8 V
LDOA2, LDOA3 –0.3 1.5 V
DIGITAL IO
DATA, CLK, CTL1–CTL6, GPO1–GPO4, IRQB –0.3 3.3 V
CHIP
Operating ambient temperature, TA –40 27 85 °C
Operating junction temperature, TJ –40 27 125 °C

4.4 Thermal Information

THERMAL METRIC(1) TPS6508700 UNIT
RSK (VQFN)
64 PINS
RθJA Junction-to-ambient thermal resistance 25.8 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 11.3 °C/W
RθJB Junction-to-board thermal resistance 4.4 °C/W
ψJT Junction-to-top characterization parameter 0.2 °C/W
ψJB Junction-to-board characterization parameter 4.4 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 0.7 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

4.5 Electrical Characteristics: Total Current Consumption

over recommended free-air temperature range and over recommended input voltage range (typical values are at TA = 25°C) (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ISD PMIC shutdown current that includes IQ for references, LDO5, LDO3P3, and digital core VSYS = 13 V, all functional output rails are disabled 65 µA

4.6 Electrical Characteristics: Reference and Monitoring System

over recommended free-air temperature range and over recommended input voltage range (typical values are at TA = 25°C) (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
REFERENCE
VREF Band-gap reference voltage 1.25 V
Band-gap reference voltage accuracy –0.5% 0.5%
CVREF Band-gap output capacitor 0.047 0.1 0.22 µF
VSYS_UVLO_5V VSYS UVLO threshold for LDO5 VSYS falling 5.24 5.4 5.56 V
VSYS_UVLO_5V_HYS VSYS UVLO threshold hysteresis for LDO5 VSYS rising above
VSYS_UVLO_5V 		200 mV
VSYS_UVLO_3V VSYS UVLO threshold for LDO3P3 VSYS falling 3.45 3.6 3.75 V
VSYS_UVLO_3V_HYS VSYS UVLO threshold hysteresis for LDO3P3 VSYS rising above
VSYS_UVLO_3V 		150 mV
TCRIT Critical threshold of die temperature TJ rising 130 145 160 °C
TCRIT_HYS Hysteresis of TCRIT TJ falling 10 °C
THOT Hot threshold of die temperature TJ rising 110 115 120 °C
THOT_HYS Hysteresis of THOT TJ falling 10 °C
LDO5
VIN Input voltage at VSYS pin 5.6 13 21 V
VOUT DC output voltage IOUT = 10 mA 4.9 5 5.1 V
IOUT DC output current 100 180 mA
IOCP Overcurrent protection Measured with output shorted to ground 200 mA
VTH_PG Power good assertion threshold in percentage of target VOUT VOUT rising 94%
VTH_PG_HYS Power good deassertion hysteresis VOUT rising or falling 4%
IQ Quiescent current VIN = 13 V, IOUT = 0 A 20 µA
COUT External output capacitance 2.7 4.7 10 µF
V5ANA-to-LDO5P0 LOAD SWITCH
RDSON On resistance VIN = 5 V, measured from V5ANA pin to LDO5P0 pin at IOUT = 200 mA 1 Ω
VTH_PG Power good threshold for external 5-V supply VV5ANA rising 4.7 V
VTH_HYS_PG Power good threshold hysteresis for external 5-V supply VV5ANA falling 100 mV
ILKG Leakage current Switch disabled,
VV5ANA = 5 V, VLDO5 = 0 V		 10 µA
LDO3P3
VIN Input voltage at VSYS pin 5.6 13 21 V
VOUT DC output voltage IOUT = 10 mA 3.3 V
DC output voltage accuracy VIN = 13 V,
IOUT = 10 mA		 –3% 3%
IOUT DC output current 40 mA
IOCP Overcurrent protection Measured with output shorted to ground 70 mA
VTH_PG Power good assertion threshold in percentage of target VOUT VOUT rising 92%
VTH_PG_HYS Power good deassertion hysteresis VOUT falling 3%
IQ Quiescent current VIN = 13 V,
IOUT = 0 A		 20 µA
COUT External output capacitance 2.2 4.7 10 µF

4.7 Electrical Characteristics: Buck Controllers

over recommended input voltage range, TA = –40°C to +85°C and TA = 25°C for typical values (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
BUCK1
VIN Power input voltage for external HSD FET 5.6 13 21 V
VFBVOUT1 Internal reference regulation voltage TA = 25°C 0.392 0.4 0.408 V
ILIM_LSD Low-side output valley current limit accuracy (programmed by external resistor RLIM) –15% 15%
ILIMREF Source current out of ILIM1 pin TA = 25°C 45 50 55 µA
VLIM Voltage at ILIM1 pin VLIM = RLIM × ILIMREF 0.2 2.25 V
VTH_PG Power good deassertion threshold in percentage of target VFB VOUT rising 105.5% 108% 110.5%
VOUT falling 89.5% 92% 94.5%
RDSON_DRVH Driver DRVH resistance Source, IDRVH = –50 mA 3 Ω
Sink, IDRVH = 50 mA 2 Ω
RDSON_DRVL Driver DRVL resistance Source, IDRVL = –50 mA 3 Ω
Sink, IDRVL = 50 mA 0.4 Ω
CBOOT Bootstrap capacitance 100 nF
RON_BOOT Bootstrap switch ON resistance 20 Ω
BUCK2, BUCK6
VIN Power input voltage for external HSD FET 5.6 13 21 V
VOUT DC output voltage VID range and options VID step size = 10 mV, BUCKx_VID[6:0] progresses from 0000001b to 1111111b 0.41 1.67 V
VID step size = 25 mV, BUCKx_VID[6:0] progresses from 0000001b to 1111111b 1 3.575 V
BUCK2 output voltage default Set by BUCK2_VID[6:0], 10-mV step size selected 0.8 V
BUCK6 output voltage default Set by BUCK6_VID[6:0], 25-mV step size selected 3.3 V
DC output voltage accuracy VOUT = 1, 1.2, 1.35, 1.5, 1.8, 2.5, 3.3 V
IOUT = 100 mA to 7 A		 –2% 2%
Total output voltage accuracy (DC plus ripple) in DCM IOUT = 10 mA, VOUT ≤ 1 V –30 40 mV
SR(VOUT) Output DVS slew rate Step size = 10 mV 2.5 3.125 mV/µs
Step size = 25 mV 5 6.25
ILIM_LSD Low-side output valley current limit accuracy (programmed by external resistor RLIM) –15% 15%
ILIMREF Source current out of ILIM1 pin TA = 25°C 45 50 55 µA
VLIM Voltage at ILIM1 pin VLIM = RLIM × ILIMREF 0.2 2.25 V
ΔVOUT/ΔVIN Line regulation VOUT = 1, 1.2, 1.35, 1.5, 1.8, 2.5, 3.3 V,
IOUT = 7 A		 –0.5% 0.5%
ΔVOUT/ΔIOUT Load regulation VIN = 13 V, VOUT = 1, 1.2, 1.35, 1.5, 1.8, 2.5,
3.3 V, IOUT = 0 A to 7 A,
referenced to VOUT at IOUT = IOUT_MAX 		0% 1%
VTH_PG Power good deassertion threshold in percentage of target VOUT VOUT rising 105.5% 108% 110.5%
VOUT falling 89.5% 92% 94.5%
RDSON_DRVH Driver DRVH resistance Source, IDRVH = –50 mA 3 Ω
Sink, IDRVH = 50 mA 2 Ω
RDSON_DRVL Driver DRVL resistance Source, IDRVL = –50 mA 3 Ω
Sink, IDRVL = 50 mA 0.4 Ω
RDIS Output auto-discharge resistance BUCKx_DIS[1:0] = 01b 100 Ω
BUCKx_DIS[1:0] = 10b 200 Ω
BUCKx_DIS[1:0] = 11b 500 Ω
CBOOT Bootstrap capacitance 100 nF
RON_BOOT Bootstrap switch ON resistance 20 Ω

4.8 Electrical Characteristics: Synchronous Buck Converters

over recommended input voltage range, TA = –40°C to +85°C and TA = 25°C for typical values (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
BUCK3, BUCK4, BUCK5
VIN Power input voltage 4.5 5 5.5 V
VOUT DC output voltage VID range and options VID step size = 25 mV, BUCKx_VID[6:0] progresses from 0000001b to 1111111b 0.425 3.575 V
BUCK3 output voltage default Set by BUCK3_VID[6:0], 25-mV step size 1.8 V
BUCK4 output voltage default Set by BUCK4_VID[6:0], 25-mV step size 0.8 V
BUCK5 output voltage default Set by BUCK5_VID[6:0], 25-mV step size 1.8 V
DC output voltage accuracy VOUT = 1, 1.2, 1.35, 1.5, 1.8,
2.5, 3.3 V, IOUT = 1.5 A		 –2% 2%
VOUT = 1, 1.2, 1.35, 1.5, 1.8,
2.5, 3.3 V, IOUT = 100 mA		 –2.5% 2.5%
Total output voltage accuracy (DC plus ripple) in DCM IOUT = 10 mA, VOUT ≤ 1 V –30 40 mV
SR(VOUT) Output DVS slew rate 5 6.25 mV/µs
IOUT Continuous DC output current 3 A
IIND_LIM HSD FET current limit 4.3 7 A
IQ Quiescent current VIN = 5 V, VOUT = 1 V 35 µA
ΔVOUT/ΔVIN Line regulation VOUT = 1, 1.2, 1.35, 1.5, 1.8,
2.5, 3.3 V, IOUT = 1.5 A		 –0.5% 0.5%
ΔVOUT/ΔIOUT Load regulation VIN = 5 V, VOUT = 1, 1.2, 1.35, 1.5, 1.8, 2.5, 3.3 V,
IOUT = 0 A to 3 A, referenced to VOUT at IOUT = 1.5 A		 –0.2% 2%
VTH_PG Power good deassertion threshold in percentage of target VOUT VOUT rising 108%
VOUT falling 92%
VTH_HYS_PG Power good reassertion hysteresis entering back into VTH_PG VOUT rising or falling 3%
RDIS Output auto-discharge resistance BUCKx_DIS[1:0] = 01b 100 Ω
BUCKx_DIS[1:0] = 10b 200
BUCKx_DIS[1:0] = 11b 500

4.9 Electrical Characteristics: LDOs

over recommended input voltage range, TA = –40°C to +85°C and TA = 25°C for typical values (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
LDOA1
VIN Input voltage 4.5 5 5.5 V
VOUT DC output voltage Set by LDOA1_VID[3:0] 3.3
Accuracy IOUT = 0 to 200 mA –2% 2% V
IOUT DC output current 200 mA
ΔVOUT/ΔVIN Line regulation IOUT = 40 mA –0.5% 0.5%
ΔVOUT/ΔIOUT Load regulation IOUT = 10 mA to 200 mA –2% 2%
IOCP Overcurrent protection VIN = 5 V, Measured with output shorted to ground 500 mA
VTH_PG Power good deassertion threshold in percentage of target VOUT VOUT rising 108%
VOUT falling 92%
tSTARTUP Start-up time Measured from EN = H to reach 95% of final value,
COUT = 4.7 µF		 500 µs
IQ Quiescent current IOUT = 0 A 23 µA
COUT External output capacitance 2.7 4.7 10 µF
ESR 100 mΩ
RDIS Output auto-discharge resistance LDOA1_DIS[1:0] = 01b 100 Ω
LDOA1_DIS[1:0] = 10b 190 Ω
LDOA1_DIS[1:0] = 11b 450 Ω
LDOA2 and LDOA3
VIN Power input voltage VOUT + VDROP (1) 1.8 1.98 V
VOUT LDOA2 DC output voltage Set by LDOA2_VID[3:0] 1.5 V
LDOA3 DC output voltage Set by LDOA3_VID[3:0] 1.2 V
DC output voltage accuracy IOUT = 0 to 600 mA –2% 3%
IOUT DC output current 600 mA
VDROP Dropout voltage VOUT = 0.99 × VOUT_NOM,
IOUT = 600 mA		 350 mV
ΔVOUT/ΔVIN Line regulation IOUT = 300 mA –0.5% 0.5%
ΔVOUT/ΔIOUT Load regulation IOUT = 10 mA to 600 mA –2% 2%
IOCP Overcurrent protection Measured with output shorted to ground 0.65 1.25 A
VTH_PG Power good assertion threshold in percentage of target VOUT VOUT rising 108%
VOUT falling 92%
tSTARTUP Start-up time Measured from EN = H to reach 95% of final value, COUT = 4.7 µF 500 µs
IQ Quiescent current IOUT = 0 A 20 µA
LDOA2 and LDOA3 (continued)
PSRR Power supply rejection ratio f = 1 kHz, VIN = 1.8 V, VOUT = 1.2 V,
IOUT = 300 mA,
COUT = 2.2 µF – 4.7 µF		 48 dB
f = 10 kHz, VIN = 1.8 V, VOUT = 1.2 V,
IOUT = 300 mA,
COUT = 2.2 µF – 4.7 µF		 30 dB
COUT External output capacitance 2.2 4.7 10 µF
ESR 100 mΩ
RDIS Output auto-discharge resistance LDOAx_DIS[1:0] = 01b 80 Ω
LDOAx_DIS[1:0] = 10b 180
LDOAx_DIS[1:0] = 11b 475
VTT LDO
VIN Power input voltage 1.2 3.3 V
VOUT DC output voltage VIN = 1.2 V, Measured at VTTFB pin VIN / 2 V
DC output voltage accuracy Relative to VIN / 2, IOUT ≤ 10 mA,
1.1 V ≤ VIN ≤ 1.35 V		 –10 10 mV
Relative to VIN / 2, IOUT ≤ 500 mA,
1.1 V ≤ VIN ≤ 1.35 V		 –25 25
IOUT DC output current sink(–) and source(+) –500 500 mA
ΔVOUT/ΔIOUT Load regulation 1.1 V ≤ VIN ≤ 1.35 V,
IOUT = –500 mA to 500 mA		 –4% 4%
IOCP Overcurrent protection Measured with output shorted to ground 0.95 A
VTH_PG Power good deassertion threshold in percentage of target VOUT VOUT rising 110%
VOUT falling 95%
VTH_HYS_PG Power good reassertion hysteresis entering back into VTH_PG 5%
IQ Total ground current VIN = 1.2 V, IOUT = 0 A 240 µA
ILKG OFF leakage current VIN = 1.2 V, disabled 1 µA
CIN External input capacitance 10 µF
COUT External output capacitance 35 µF
RDIS Output auto-discharge resistance VTT_DIS = 0b 1000 kΩ
VTT_DIS = 1b 60 80 100 Ω
(1) It must be equal to or greater than 1.62 V.

4.10 Electrical Characteristics: Load Switches

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SWA1
VIN Input voltage range 0.5 1.5 3.3 V
IOUT DC output current 300 mA
RDSON ON resistance VIN = 1.8 V, measured from PVINSWA1 pin to SWA1 pin at IOUT = IOUT,MAX 60 93 mΩ
VIN = 3.3 V, measured from PVINSWA1 pin to SWA1 pin at IOUT = IOUT,MAX 100 165
VTH_PG Power good deassertion threshold in percentage of target VOUT VOUT rising 108%
VOUT falling 92%
VTH_HYS_PG Power good reassertion hysteresis entering back into VTH_PG VOUT rising or falling 2%
IINRUSH Inrush current upon turnon VIN = 3.3 V, COUT = 0.1 µF 10 mA
IQ Quiescent current VIN = 3.3 V, IOUT = 0 A 10.5 µA
VIN = 1.8 V, IOUT = 0 A 9
ILKG Leakage current Switch disabled, VIN = 1.8 V 7 370 nA
Switch disabled, VIN = 3.3 V 10 900
COUT External output capacitance 0.1 µF
RDIS Output auto-discharge resistance SWA1_DIS[1:0] = 01 100 Ω
SWA1_DIS[1:0] = 10 200
SWA1_DIS[1:0] = 11 500
SWB1, SWB2
VIN Input voltage range 0.5 1.5 3.3 V
IOUT DC current per channel 400 mA
RDSON ON resistance per channel VIN = 1.8 V, measured from PVINSWB1_B2 pin to SWB1/SWB2 pin at IOUT = IOUT,MAX 68 92 mΩ
VIN = 3.3 V, measured from PVINSWB1_B2 pin to SWB1/SWB2 pin at IOUT = IOUT,MAX 75 125 mΩ
VTH_PG Power good deassertion threshold in percentage of target VOUT VOUT rising 108%
VOUT falling 92%
VTH_HYS_PG Power good reassertion hysteresis entering back into VTH_PG VOUT rising or falling 2%
IINRUSH Inrush current upon turning on VIN = 3.3 V, COUT = 0.1 µF 10 mA
IQ Quiescent current VIN = 3.3 V, IOUT = 0 A 10.5 µA
VIN = 1.8 V, IOUT = 0 A 9
ILKG Leakage current Switch disabled, VIN = 1.8 V 7 460 nA
Switch disabled, VIN = 3.3 V 10 1150
COUT External output capacitance 0.1 µF
RDIS Output auto-discharge resistance SWBx_DIS[1:0] = 01 100 Ω
SWBx_DIS[1:0] = 10 200
SWBx_DIS[1:0] = 11 500

4.11 Digital Signals: I2C Interface

over recommended free-air temperature range and over recommended input voltage range (typical values are at TA = 25°C) (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOL Low-level output voltage VPULL_UP = 1.8 V 0.4 V
VIH High-level input voltage 1.2 V
VIL Low-level input voltage 0.4 V
ILKG Leakage current VPULL_UP = 1.8 V 0.01 0.3 µA
RPULL-UP Pullup resistance Standard mode 8.5 kΩ
Fast mode 2.5
Fast mode plus 1
COUT Total load capacitance per pin 50 pF

4.12 Digital Input Signals (CTLx)

over recommended free-air temperature range and over recommended input voltage range (typical values are at TA = 25°C) (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIH High-level input voltage 0.85 V
VIL Low-level input voltage 0.4 V

4.13 Digital Output Signals (IRQB, GPOx)

over recommended free-air temperature range and over recommended input voltage range (typical values are at TA = 25°C) (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOL Low-level output voltage IOL < 2 mA 0.4 V
ILKG Leakage current VPULL_UP = 1.8 V 0.35 µA

4.14 Timing Requirements

over recommended free-air temperature range and over recommended input voltage range (typical values are at TA = 25°C) (unless otherwise noted)
MIN NOM MAX UNIT
I2C INTERFACE
fCLK Clock frequency (standard mode) 100 kHz
Clock frequency (fast mode) 400 kHz
Clock frequency (fast mode plus) 1000 kHz
tr Rise time (standard mode) 1000 ns
Rise time (fast mode) 300 ns
Rise time (fast mode plus) 120 ns
tf Rise time (standard mode) 300 ns
Rise time (fast mode) 300 ns
Rise time (fast mode plus) 120 ns

4.15 Switching Characteristics

over operating free-air temperature range and over recommended input voltage range (typical values are at TA = 25°C) (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
BUCK CONTROLLERS
tPG Total turnon time Measured from enable going high to when output reaches 90% of target value. 550 850 µs
TON,MIN Minimum on-time of DRVH 50 ns
TDEAD Driver dead-time DRVH off to DRVL on 15 ns
DRVL off to DRVH on 30 ns
fSW Switching frequency Continuous-conduction mode,
VIN = 13 V, VOUT ≥ 1 V		 1000 kHz
BUCK CONVERTERS
tPG Total turnon time Measured from enable going high to when output reaches 90% of target value. 250 1000 µs
fSW Switching frequency Continuous-conduction mode, VOUT = 1 V, IOUT = 1 A 1.6 MHz
Continuous-conduction mode, VOUT = 1.05 V, IOUT = 1 A 1.7 MHz
Continuous-conduction mode, VOUT = 1.24 V, IOUT = 1 A 1.9 MHz
Continuous-conduction mode, VOUT = 1.35 V, IOUT = 1 A 2 MHz
Continuous-conduction mode, VOUT = 1.8 V, IOUT = 1 A 2.5 MHz
LDOAx
tSTARTUP Start-up time Measured from enable going high to when output reaches 95% of final value,
VOUT = 1.2 V, COUT = 4.7 µF		 180 µs
VTT LDO
tSTARTUP Start-up time Measured from enable going high to PG assertion,
VOUT = 0.675 V, COUT = 40 µF		 22 µs
SWA1
tTURN-ON Turnon time Measured from enable going high to reach 95% of final value,
VIN = 3.3 V, COUT = 0.1 µF		 0.85 ms
Measured from enable going high to reach 95% of final value,
VIN = 1.8 V, COUT = 0.1 µF		 0.63 ms
SWB1_2
tTURN-ON Turnon time Measured from enable going high to reach 95% of final value,
VIN = 3.3 V, COUT = 0.1 µF		 1.1 ms
Measured from enable going high to reach 95% of final value,
VIN = 1.8 V, COUT = 0.1 µF		 0.82 ms

4.16 Typical Characteristics

Measurements done at 25°C.
TPS6508700 AC_03_swcs129.gif
Figure 4-1 BUCK2 Controller Start Up to 1 V by I2C
TPS6508700 D011_SWCS128.gif
Figure 4-3 BUCK6 Efficiency at VIN = 13 V
TPS6508700 D009_SWCS128.gif
Figure 4-5 Converter Efficiency at VIN = 5 V
TPS6508700 AC_04_swcs129.gif
Figure 4-2 Converter Start Up to 1 V by I2C
TPS6508700 D012_SWCS128.gif
Figure 4-4 BUCK6 Efficiency at VIN = 18 V