JAJSVA1F May   2012  – August 2024 TPS65131-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Conversion
      2. 7.3.2 Control
      3. 7.3.3 Output Rails Enable or Disable
      4. 7.3.4 Load Disconnect
      5. 7.3.5 Soft Start
      6. 7.3.6 Overvoltage Protection
      7. 7.3.7 Undervoltage Lockout
      8. 7.3.8 Overtemperature Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-Save Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 TPS65131-Q1 With VPOS = 10.5V, VNEG = –10V
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
        1. 8.2.3.1 Programming the Output Voltage
          1. 8.2.3.1.1 Boost Converter
          2. 8.2.3.1.2 Inverting Converter
          3. 8.2.3.1.3 Inductor Selection
        2. 8.2.3.2 Capacitor Selection
          1. 8.2.3.2.1 Input Capacitor
          2. 8.2.3.2.2 Output Capacitors
        3. 8.2.3.3 Rectifier Diode Selection
        4. 8.2.3.4 External P-MOSFET Selection
        5. 8.2.3.5 Stabilizing the Control Loop
          1. 8.2.3.5.1 Feedforward Capacitors
          2. 8.2.3.5.2 Compensation Capacitors
      4. 8.2.4 Analog Supply Input Filter
        1. 8.2.4.1 RC-Filter
        2. 8.2.4.2 LC-Filter
      5. 8.2.5 Thermal Information
      6. 8.2.6 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 ドキュメントの更新通知を受け取る方法
    2. 9.2 サポート・リソース
    3. 9.3 商標
    4. 9.4 静電気放電に関する注意事項
    5. 9.5 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Mechanical Data
    2. 11.2 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

TPS65131-Q1 TPS65131-Q1
Figure 5-1 24-pin VQFN Bottom View
Figure 5-2 24-pin VQFN Top View
Table 5-1 Pin Functions
PIN I/O DESCRIPTION
NAME NO.
AGND 19 — Analog ground pin
BSW 7 O Gate-control pin for external battery switch. This pin goes low when ENP is set high.
CN 18 I/O Compensation pin for inverting converter control
CP 21 I/O Compensation pin for boost converter control
ENN 10 I Enable pin for the negative-output voltage (0V: disabled, VIN: enabled)
ENP 8 I Enable pin for the positive-output voltage (0V: disabled, VIN: enabled)
FBN 16 I Feedback pin for the negative-output voltage divider
FBP 22 I Feedback pin for the positive-output voltage divider
INN 5, 6 O Inverting converter switch pin
INP 1, 24 O Boost converter switch pin
NC(1) 12, 20 — Not connected
OUTN 13, 14 I/O Inverting converter switch output
PGND 2, 3 — Power ground pin
PSN 11 I Power-save mode enable for inverter stage (0V: disabled, VIN: enabled)
PSP 9 I Power-save mode enable for boost converter stage (0V: disabled, VIN: enabled)
VIN 4 I Control supply input
VNEG 15 I Negative-output voltage-sense input
VPOS 23 I Positive-output voltage-sense input
VREF 17 O Reference output voltage. Bypass this pin with a 220nF capacitor to ground. Connect the lower resistor of the negative-output voltage divider to this pin.
Thermal pad Thermal pad for thermal performance, connect to PGND
(1) NC - No internal connection