SLVSBB2F May 2012 – August 2024 TPS65131-Q1
PRODUCTION DATA
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Figure 5-1 24-pin VQFN Bottom View
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Figure 5-2 24-pin VQFN
Top View
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PIN | I/O | DESCRIPTION | |
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NAME | NO. | ||
AGND | 19 | — | Analog ground pin |
BSW | 7 | O | Gate-control pin for external battery switch. This pin goes low when ENP is set high. |
CN | 18 | I/O | Compensation pin for inverting converter control |
CP | 21 | I/O | Compensation pin for boost converter control |
ENN | 10 | I | Enable pin for the negative-output voltage (0V: disabled, VIN: enabled) |
ENP | 8 | I | Enable pin for the positive-output voltage (0V: disabled, VIN: enabled) |
FBN | 16 | I | Feedback pin for the negative-output voltage divider |
FBP | 22 | I | Feedback pin for the positive-output voltage divider |
INN | 5, 6 | O | Inverting converter switch pin |
INP | 1, 24 | O | Boost converter switch pin |
NC(1) | 12, 20 | — | Not connected |
OUTN | 13, 14 | I/O | Inverting converter switch output |
PGND | 2, 3 | — | Power ground pin |
PSN | 11 | I | Power-save mode enable for inverter stage (0V: disabled, VIN: enabled) |
PSP | 9 | I | Power-save mode enable for boost converter stage (0V: disabled, VIN: enabled) |
VIN | 4 | I | Control supply input |
VNEG | 15 | I | Negative-output voltage-sense input |
VPOS | 23 | I | Positive-output voltage-sense input |
VREF | 17 | O | Reference output voltage. Bypass this pin with a 220nF capacitor to ground. Connect the lower resistor of the negative-output voltage divider to this pin. |
Thermal pad | Thermal pad for thermal performance, connect to PGND |