JAJSOJ1E March   2004  – April 2022 TPS65130 , TPS65131

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Conversion
      2. 7.3.2 Control
      3. 7.3.3 Enable
      4. 7.3.4 Load Disconnect
      5. 7.3.5 Soft-Start
      6. 7.3.6 Overvoltage Protection
      7. 7.3.7 Undervoltage Lockout
      8. 7.3.8 Overtemperature Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-Save Mode
      2. 7.4.2 Full Operation with VIN > 2.7 V
      3. 7.4.3 Limited Operation with VUVLO < VIN < 2.7 V
      4. 7.4.4 No Operation with VIN < VUVLO
  8. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Programming the Output Voltage
          1. 8.2.2.1.1 Boost Converter
          2. 8.2.2.1.2 Inverting Converter
        2. 8.2.2.2 Inductor Selection
        3. 8.2.2.3 Capacitor Selection
          1. 8.2.2.3.1 Input Capacitor
          2. 8.2.2.3.2 Output Capacitors
        4. 8.2.2.4 Rectifier Diode Selection
        5. 8.2.2.5 External PMOS Selection
        6. 8.2.2.6 Stabilizing the Control Loop
          1. 8.2.2.6.1 Feedforward Capacitor
          2. 8.2.2.6.2 Compensation Capacitors
      3. 8.2.3 Analog Supply Filter
        1. 8.2.3.1 RC-Filter
        2. 8.2.3.2 LC-Filter
      4. 8.2.4 Application Curves
        1.       Power Supply Recommendations
  9. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
    3. 9.3 Thermal Considerations
  10. 10Device and Documentation Support
    1. 10.1 Device Support
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RGE|24
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

GUID-00FE0B34-E7B4-4B24-B56D-795DE6C8B0F1-low.gif Figure 5-1 RGE Package, 24-PIN VQFN (Top View)
Table 5-1 Pin Functions
PIN TYPE DESCRIPTION
NAME NO.
AGND 19 — Analog ground pin
BSW 7 O Gate control pin for external battery switch. This pin goes low when ENP is set high.
CN 18 — Compensation pin for inverting converter control
CP 21 — Compensation pin for boost converter control
ENN 10 I Enable pin for the negative output voltage (0 V: disabled, VIN: enabled)
ENP 8 I Enable pin for the positive output voltage (0 V: disabled, VIN: enabled)
FBN 16 I Feedback pin for the negative output voltage divider
FBP 22 I Feedback pin for the positive output voltage divider
INN 5, 6 I Inverting converter switch input
INP 1, 24 I Boost converter switch input.
NC 12, 20 — Not connected
OUTN 13, 14 O Inverting converter switch output.
PGND 2, 3 — Power ground pin
PSN 11 I Power-save mode enable for inverter stage (0 V: disabled, VIN: enabled)
PSP 9 I Power-save mode enable for boost converter stage (0 V: disabled, VIN: enabled)
VIN 4 I Control supply input
VNEG 15 I Negative output voltage sense input
VPOS 23 I Positive output voltage sense input
VREF 17 O Reference output voltage. Bypass this pin with a 220-nF capacitor to ground. Connect the lower resistor of the negative output voltage divider to this pin