JAJSEP8D April   2012  – February 2018 TPS65197

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     概略回路図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Sequencing
      2. 7.3.2 Power Up
      3. 7.3.3 Power Down
      4. 7.3.4 Disabling the Discharge Function
      5. 7.3.5 Undervoltage Lockout
      6. 7.3.6 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Output Clock Behavior
      2. 7.4.2 Charge-Sharing Methods TPS65197
      3. 7.4.3 Charge-Sharing Methods TPS65197B
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 関連リンク
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

V(GH) = 30 V, V(GL1) = –10 V, V(GL2) = –8 V, TA = –40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V(GH) Input voltage range V(GH) 16.5 45 V
V(GL1) Input voltage range V(GL1) –20 –3
V(GL2) Input voltage range V(GL2) –20 –3
I(GH) Positive supply current CLKINx = STVIN = RESETIN = SEL_CS = 0 V, DIS_SENSE = 5 V 0.3 1 mA
I(GL1) Negative supply current –0.5 –0.05
I(GL2) Negative supply current –0.5 –0.05
V(UVLO) Undervoltage lockout threshold V(GH) rising, TJ = –40ºC to 85ºC 13.5 15 16.5 V
V(GH) falling, TJ = –40ºC to 85ºC 2 3.5 5
T(SD) Thermal shutdown temperature TJ rising 130 150 170 °C
INPUT SIGNALS (CLKINx, STVIN, RESETIN, SEL_CS, DIS_SENSE)
VIH High-level input voltage CLKINx, STVIN, RESETIN Input rising 1.65 V
VIL Low-level input voltage CLKINx, STVIN, RESETIN Input falling 0.8
V(SEL_CS) Charge-sharing-disabled voltage 0.5
3-Channel Charge-Sharing voltage 1 2
2-Channel Charge-Sharing voltage 2.8 6.5
V(DIS_SENSE) Discharge detection threshold V(DIS_SENSE) falling, TJ = 0ºC to 85ºC 1.17 1.26 1.36
IIN Input current CLKINx, STVIN, RESETIN, DIS_SENSE CLKINx = STVIN = RESETIN = DIS_SENSE = 5 V 2 100 nA
Input current SEL_CS SEL_CS = 5 V 50 100 µA
R(SEL_CS) SEL_CS pin, internal pulldown resistance 50 100 150 kΩ
LEVEL SHIFTERS (CLKOUT1 to CLKOUT6)
rDS(on) High-side on-resistance, CLKOUTx I(OUT) = 10 mA, sourcing (high side) 11 25 Ω
Low-side on-resistance, CLKOUTx I(OUT) = 10 mA, sinking (low side) 7 15
R(CS) Internal charge-sharing resistance I(CS) = 10 mA, TJ = –40ºC to 85ºC 30 60 100
LEVEL SHIFTERS (STVOUT, RESETOUT)
rDS(on) High-side on-resistance STVOUT, RESETOUT I(OUT) = 10 mA, sourcing (high side) 30 60 Ω
Low-side on-resistance STVOUT, RESETOUT I(OUT) = 10 mA, sinking (low side) 15 30
DISCHARGE OUTPUTS (DISCH1, DISCH2)
rDS(on) High-side on-resistance, DISCH1 I(OUT) = 10 mA, sourcing (high side) 14 60 Ω
Low-side on-resistance DISCH1 I(OUT) = 10 mA, sinking (low side) 3 10
High-side on-resistance, DISCH2 I(OUT) = 10 mA, sourcing (high side) 14 60
Low-side on-resistance DISCH2 I(OUT) = 10 mA, sinking (low side) 10 20