JAJSEP8D April   2012  – February 2018 TPS65197

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     概略回路図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Sequencing
      2. 7.3.2 Power Up
      3. 7.3.3 Power Down
      4. 7.3.4 Disabling the Discharge Function
      5. 7.3.5 Undervoltage Lockout
      6. 7.3.6 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Output Clock Behavior
      2. 7.4.2 Charge-Sharing Methods TPS65197
      3. 7.4.3 Charge-Sharing Methods TPS65197B
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 関連リンク
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.3 Power Down

When the discharge-sense (DIS_SENSE) voltage falls below its typical threshold voltage of 1.26 V, all clock output channels follow VGH until VGH falls below its typical falling UVLO threshold voltage of 3.5 V; then all clock output channels and DISCH1 follow VGL1, DISCH2 follows VGL2. Once discharge-sense is triggered the state is latched, to reset and continue normal operation VGH has to fall below the falling UVLO threshold of 3.5 V.

In case the discharge-sense (DIS_SENSE) voltage stays high during power down, all clock output channels follow their input signals until VGH falls below its typical falling UVLO threshold voltage of 3.5 V; then all clock output channels follow VGL1. The discharge channels follow VGL1 and VGL2 all the time.