JAJSEP8D April   2012  – February 2018 TPS65197

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     概略回路図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Sequencing
      2. 7.3.2 Power Up
      3. 7.3.3 Power Down
      4. 7.3.4 Disabling the Discharge Function
      5. 7.3.5 Undervoltage Lockout
      6. 7.3.6 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Output Clock Behavior
      2. 7.4.2 Charge-Sharing Methods TPS65197
      3. 7.4.3 Charge-Sharing Methods TPS65197B
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 関連リンク
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

RUY Package
28-Pin WQFN With Thermal Pad
Top View
TPS65197 TPS65197B pinout.gif

Pin Functions

PIN I/O/P DESCRIPTION
NAME NUMBER
CLKIN1 20 I Clock 1 input
CLKIN2 19 I Clock 2 input
CLKIN3 18 I Clock 3 input
CLKIN4 17 I Clock 4 input
CLKIN5 16 I Clock 5 input
CLKIN6 15 I Clock 6 input
CLKOUT1 22 I/O Clock 1 output
CLKOUT2 24 I/O Clock 2 output
CLKOUT3 26 I/O Clock 3 output
CLKOUT4 28 I/O Clock 4 output
CLKOUT5 2 I/O Clock 5 output
CLKOUT6 3 I/O Clock 6 output
CS_1 23 I/O Clock 1 charge-sharing input
CS_2 25 I/O Clock 2 charge-sharing input
CS_3 27 I/O Clock 3 charge-sharing input
CS_4 1 I/O Clock 4 charge-sharing input
DISCH1 7 I/O Discharge 1 output. Internally connected to VGL1 and VGH
DISCH2 6 I/O Discharge 2 output. Internally connected to VGL2 and VGH
DIS_SENSE 13 I Discharge sense terminal
GND 9 – Ground
RESETIN 14 I RESET input
RESETOUT 5 I/O RESET output
SEL_CS 12 I Charge-sharing method-selection terminal. When left floating or pulled to GND, charge-sharing is disabled.
STVIN 21 I STV input
STVOUT 4 I/O STV output
VGH 8 P Positive supply voltage. Place a buffer capacitor close to this terminal.
VGL1 10 P Negative supply voltage for all outputs except discharge 2. Place a buffer capacitor close to this terminal.
VGL2 11 P Negative supply voltage for discharge 2
Thermal pad – – The thermal pad is connected to VGL1.