JAJSK46A November   2020  – August 2021 TPS6521845

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     4
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Wake-Up and Power-Up and Power-Down Sequencing
        1. 7.3.1.1  Power-Up Sequencing
        2. 7.3.1.2  Power-Down Sequencing
        3. 7.3.1.3  Strobe 1 and Strobe 2
        4. 7.3.1.4  Supply Voltage Supervisor and Power-Good (PGOOD)
        5. 7.3.1.5  Backup Supply Power-Good (PGOOD_BU)
        6. 7.3.1.6  Internal LDO (INT_LDO)
        7. 7.3.1.7  Current Limited Load Switches
          1. 7.3.1.7.1 Load Switch 1 (LS1)
          2. 7.3.1.7.2 Load Switch 2 (LS2)
          3. 7.3.1.7.3 Load Switch 3 (LS3)
        8. 7.3.1.8  LDO1
        9. 7.3.1.9  Coin Cell Battery Voltage Acquisition
        10. 7.3.1.10 UVLO
        11. 7.3.1.11 Power-Fail Comparator
        12. 7.3.1.12 Battery-Backup Supply Power-Path
        13. 7.3.1.13 DCDC3 and DCDC4 Power-Up Default Selection
        14. 7.3.1.14 I/O Configuration
          1. 7.3.1.14.1 Configuring GPO2 as Open-Drain Output
          2. 7.3.1.14.2 Using GPIO3 as Reset Signal to DCDC1 and DCDC2
        15. 7.3.1.15 Push Button Input (PB)
          1. 7.3.1.15.1 Signaling PB-Low Event on the nWAKEUP Pin
          2. 7.3.1.15.2 Push Button Reset
        16. 7.3.1.16 AC_DET Input (AC_DET)
        17. 7.3.1.17 Interrupt Pin (INT)
        18. 7.3.1.18 I2C Bus Operation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Modes of Operation
      2. 7.4.2 OFF
      3. 7.4.3 ACTIVE
      4. 7.4.4 SUSPEND
      5. 7.4.5 RESET
    5. 7.5 Register Maps
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Applications Without Battery Backup Supplies
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Output Filter Design
        2. 8.2.2.2 Inductor Selection for Buck Converters
        3. 8.2.2.3 Output Capacitor Selection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.1.2 Power-Down Sequencing

By default, the power-down sequence follows the reverse of the power-up sequence. When the power-down sequence is triggered, STROBE 10 occurs and any rail assigned to STROBE 10 is shut down and its discharge circuit is enabled. After a delay time of DLY9, STROBE 9 occurs and any rail assigned to it is shut down and its discharge circuit is enabled. The sequence continues until all strobes occur and all DLYx times execute. The DLYx times are extended by a factor of 10x to provide ample time for discharge, and preventing output voltages from crossing during shut-down. The DLYFCTR bit is applied globally to all power-down delay times. Regardless of the DLYx and DLYFCTR settings, the PMIC enters OFF, SUSPEND, or RECOVERY state 500 ms after the power-down sequence initiates, to ensure that the discharge circuits remain enabled for a minimum of 150 ms before the next power-up sequence starts.

A power-down sequence executes if one of the following events occurs:

  • The device is in the WAIT_PWR_EN state, the PB and AC_DET pins are high, PWR_EN is low, and the 20-s timer has expired.
  • The device is in the ACTIVE state and the PWR_EN pin is pulled low.
  • The device is in the WAIT_PWR_EN, ACTIVE, or SUSPEND state and the push-button is held low for > 8 s (15 s if TRST = 1b).
  • A fault occurs in the device (OTS, UVLO, PGOOD failure).

When transitioning from ACTIVE to SUSPEND state, the rails not controlled by the power-down sequencer maintains the same ON/OFF state in SUSPEND state that it had in ACTIVE state. This allows for the selected power rails to remain powered up when in the SUSPEND state.

When transitioning to the OFF or RECOVERY state, rails not under sequencer control are shut-down as follows:

  • DCDC1, DCDC2, DCDC3, DCDC4, LDO1, and LS1 shut down at the beginning of the power-down sequence, if not under sequencer control (SEQ = 0b).
  • LS2 and LS3 shut down as the state machine enters an OFF or RECOVERY state; 500 ms after the power-down sequence is triggered.

If the supply voltage on IN_BIAS drops below 2.5 V, the digital core is reset and all power rails are shut down instantaneously and are pulled low to ground by their internal discharge circuitry (DCDC1-4, and LDO1). The amount of time the discharge circuitry remains active is a function of the INT_LDO hold up time (see Section 7.3.1.6 for more details).