Power-good (PGOOD) is an open-drain output of the built-in voltage supervisor that monitors DCDC1, DCDC2, DCDC3, DCDC4, and LDO1. The output is Hi-Z when all enabled rails are in regulation and driven low when one or more rails encounter a fault which brings the output voltage outside the specified tolerance range. In a typical application PGOOD drives the reset signal of the SOC.

Figure 7-7 Definition of Undervoltage, Overvoltage Thresholds, Hysteresis, and Deglitch Times

The following rules apply to the PGOOD output:

• The power-up default state for THE PGOOD is low. When all rails are disabled, the PGOOD output is driven low.
• Only enabled rails are monitored. Disabled rails are ignored.
• Power-good monitoring of a particular rail starts 5 ms after the rail is enabled and is continuously monitored thereafter. This allows the rail to power-up.
• The PGOOD is delayed by PGDLY time after the sequencer is finished and the last rail is enabled.
• If an enabled rail is continuously outside the monitoring threshold for longer than the deglitch time, then the PGOOD is pulled low, and all rails are shut-down following the power-down sequence. PGDLY does not apply.
• Disabling a rail manually by resetting the DCx_EN or LDO1_EN bit has no effect on the PGOOD pin. If all rails are disabled, the PGOOD is driven low as the last rail is disabled.
• If the power-down sequencer is triggered, PGOOD is driven low.
• The PGOOD is driven low in the SUSPEND state, regardless of the number of rails that are enabled.

Figure 7-8 shows a typical power-up sequence and PGOOD timing.

A. (1) Sequence shown for TPS65218D0 variant. For other TPS65218xx variants, refer to registers SEQ1-7 in Section 5.6.4 for factory programmed sequence order and timing.

Figure 7-8 Typical Power-Up Sequence of the Main Output Rails