JAJSK46A November   2020  – August 2021 TPS6521845

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     4
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Wake-Up and Power-Up and Power-Down Sequencing
        1. 7.3.1.1  Power-Up Sequencing
        2. 7.3.1.2  Power-Down Sequencing
        3. 7.3.1.3  Strobe 1 and Strobe 2
        4. 7.3.1.4  Supply Voltage Supervisor and Power-Good (PGOOD)
        5. 7.3.1.5  Backup Supply Power-Good (PGOOD_BU)
        6. 7.3.1.6  Internal LDO (INT_LDO)
        7. 7.3.1.7  Current Limited Load Switches
          1. 7.3.1.7.1 Load Switch 1 (LS1)
          2. 7.3.1.7.2 Load Switch 2 (LS2)
          3. 7.3.1.7.3 Load Switch 3 (LS3)
        8. 7.3.1.8  LDO1
        9. 7.3.1.9  Coin Cell Battery Voltage Acquisition
        10. 7.3.1.10 UVLO
        11. 7.3.1.11 Power-Fail Comparator
        12. 7.3.1.12 Battery-Backup Supply Power-Path
        13. 7.3.1.13 DCDC3 and DCDC4 Power-Up Default Selection
        14. 7.3.1.14 I/O Configuration
          1. 7.3.1.14.1 Configuring GPO2 as Open-Drain Output
          2. 7.3.1.14.2 Using GPIO3 as Reset Signal to DCDC1 and DCDC2
        15. 7.3.1.15 Push Button Input (PB)
          1. 7.3.1.15.1 Signaling PB-Low Event on the nWAKEUP Pin
          2. 7.3.1.15.2 Push Button Reset
        16. 7.3.1.16 AC_DET Input (AC_DET)
        17. 7.3.1.17 Interrupt Pin (INT)
        18. 7.3.1.18 I2C Bus Operation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Modes of Operation
      2. 7.4.2 OFF
      3. 7.4.3 ACTIVE
      4. 7.4.4 SUSPEND
      5. 7.4.5 RESET
    5. 7.5 Register Maps
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Applications Without Battery Backup Supplies
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Output Filter Design
        2. 8.2.2.2 Inductor Selection for Buck Converters
        3. 8.2.2.3 Output Capacitor Selection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.4.2 OFF

In OFF mode, the PMIC is completely shut down with the exception of a few circuits to monitor the AC_DET, PWR_EN, and PB input. All power rails are turned off and the registers are reset to their default values. The I2C communication interface is turned off. This is the lowest-power mode of operation. To exit OFF mode VIN_BIAS must exceed the UVLO threshold and one of the following wake-up events must occur:

  • The PB input is pulled low.
  • THE AC_DET input is pulled low.
  • The PWR_EN input is pulled high.

To enter the OFF state, ensure that all power rails are assigned to the sequencer, then pull the PWR_EN pin low. Additionally, if the OFFnPFO bit is set to 1b and the PFI input falls below the power fail threshold the device transitions to the OFF state. If the freshness seal is broken, DCDC5 and DCDC6 remains on in the OFF state. If a PGOOD or OTS fault occurs while in the ACTIVE state, TPS6521845 will transition to the RESET state.