JAJSE75B December 2017 – September 2018 TPS65218D0
UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.
The FSEAL (freshness seal) bit prevents accidental shut-down of the always-on supplies, DCDC5 and DCDC6. The FSEAL bit exists in a default state of 0, and can be set to 1 and reset to 0 once for factory testing. The second time the bit is set to 1, it remains 1 and cannot reset again under software control. Coin-cell battery and main supply must be disconnected from the IC to reset the FSEAL bit again. With the FSEAL bit set to 1, DCDC5 and DCDC6 are forced ON regardless of the state of the DC5_EN and DC6_EN bit, and the rails do not turn off when the IC enters OFF mode.
A consecutive write of [0xB1, 0xFE, 0xA3] to the password register sets the FSEAL bit to 1. The three bytes must be written consecutively for the sequence to be valid. No other read or write transactions are allowed between the three bytes, or the sequence is invalid. After a valid sequence, the FSEAL bit in the STATUS register reflects the new setting.
After setting the FSEAL bit, the IC can enter OFF or any other mode of operation without affecting the state of the FSEAL bit, provided the coin-cell supply remains connected to the chip.
A second write of [0xB1, 0xFE, 0xA3] to the password register resets the FSEAL bit to 0. The three bytes must be written consecutively for the sequence to be valid.
A third write of [0xB1, 0xFE, 0xA3] to the password register sets the FSEAL bit to 1 and locks it into this state for as long as the coin-cell supply (CC) remains connected to the chip.