JAJSE75B December 2017 – September 2018 TPS65218D0
UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.
Register mask: C0h
STATUS is shown in Figure 5-41 and described in Table 5-13.
Return to Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FSEAL | EE | AC_STATE | PB_STATE | STATE | CC_STAT | ||
R-0b | R-0b | R-X | R-X | R-X | R-X |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | FSEAL | R | 0b |
Freshness seal (FSEAL) status. Note: See Section 5.6.2 for details. 0b = FSEAL is in native state (fresh) 1b = FSEAL is broken |
6 | EE | R | 0b |
EEPROM status 0b = EEPROM values have not been changed from factory default setting 1b = EEPROM values have been changed from factory default settings |
5 | AC_STATE | R | X |
AC_DET input status bit 0b = AC_DET input is inactive (AC_DET input pin is high) 1b = AC_DET input is active (AC_DET input is low) |
4 | PB_STATE | R | X |
PB input status bit 0b = Push Button input is inactive (PB input pin is high) 1b = Push Button input is active (PB input pin is low) |
3-2 | STATE | R | X |
State machine STATE indication 0h = PMIC is in transitional state 1h = PMIC is in WAIT_PWR_EN state 2h = PMIC is in ACTIVE state 3h = PMIC is in SUSPEND state |
1-0 | CC_STAT | R | X |
Coin cell state of charge. Note: Coin-cell voltage acquisition must be triggered first before status bits are valid. See CC_AQ bit in Section 5.6.4.7. 0h = VCC < VLOW_LEVEL; Coin cell is not present or approaching end-of-life (EOL) 1h = VLOW_LEVEL < VCC < VGOOD_LEVEL; Coin cell voltage is LOW. 2h = VGOOD_LEVEL < VCC <VIDEAL_LEVEL; Coin cell voltage is GOOD. 3h = VIDEAL < VCC; Coin cell voltage is IDEAL. |