The TPS65219-Q1 integrates three buck converters. Buck1 is capable of supporting up to 3.5 A and Buck2/Buck3 are capable of supporting up to 2 A of load current. The buck converters have an input voltage range from 2.5 V to 5.5 V, and can be connected either directly to the system power or the output of a another buck converter. The output voltage is programmable in the range of 0.6 V to 3.4 V: in 25mV-steps up to 1.4V, in 100mV-steps between 1.4V and 3.4V.

• The ON/OFF state of the buck converters in ACTIVE state is controlled by the corresponding BUCKx_EN bit in the ENABLE_CTRL register.
• The ON/OFF state of the buck converters in STBY state is controlled by the corresponding BUCKx_STBY_EN bit in the STBY_1_CONFIG register.
• In INITIALIZE state, the buck converters are off, regardless of bit-settings.

• The converters activity can be controlled by the sequencer or through I2C communication.

• Fixed frequency mode
  • The converters can be forced into fixed frequency mode for best EMI-control by setting bit BUCK_FF_ENABLE bit in BUCKS_CONFIG register. If fixed-frequency mode is enabled, the regulators also support optional spread-spectrum. Spread-spectrum can be enabled by setting bit BUCK_SS_ENABLE in BUCKS_CONFIG register. Both of these settings are global for all three buck converters. If fixed-frequency mode is enabled, the regulators support individual out-of-phase switching: the phase-relation of the buck rails can be configured in 90°-steps in relation to the phase of Buck1 by BUCKx_PHASE_CONFIG in the BUCKS_CONFIG register. This bit must only change when this regulator is disabled.
• Quasi-fixed-frequency mode
  • The converters can operate in forced-PWM mode, irrespective of load-current, or can be allowed to enter pulse-frequency-modulation (PFM) for low load-currents. The mode is controlled by either the MODE/STBY pin or the MODE/RESET pin if either of those is configured as 'MODE', or by an I2C-command to MODE_I2C_CTRL bit in MFP_1_CONFIG register (see pin-configuration and I2C-command in 'PWM/PFM and Low Power Modes (MODE/STBY)' and PWM/PFM and Reset (MODE/RESET)' section.
  • During a transition to ACTIVE state or to INITIALIZE state, the buck converters are forced to PWM, irrespective of the pin-state. PFM-entry is only allowed when the device enters ACTIVE state, upon completion of the sequence and expiration of the last power-up-slot.
  • In case of a DVFS-induced output voltage change, the TPS65219-Q1 temporarily forces the buck-regulators into PWM until the voltage change completed. If PFM is allowed, the entry and exit into PFM is load-current dependent. PFM starts when the inductor current reaches 0 A, which is the case at a load current approximately calculated by:

  • I_LOAD = {[(V_{PVIN_Bx} - V_BUCKx) / L] × (V_BUCKx / V_{PVIN_Bx}) × (1 / f_SW)} / 2

• The converters can be individually configured further for a high-bandwidth-mode for optimum transient-response or lower bandwidth, allowing minimum output filter capacitance. The selection is done by the BUCKx_BW_SEL bits in GENERAL_CONFIG register and is available for both configurations, fixed-frequency and quasi-fixed-frequency. This bit must only change if this regulator is disabled. Please note the higher output-capacitance requirements for high bandwidth use case!
• If VSEL_SD/VSEL_DRR is configured as 'VSEL_DDR' by the VSEL_DDR_SD bit in MFP_1_CONFIG register, the output voltage of Buck3 can be controlled by pulling the VSEL_SD/VSEL_DDR pin high, low or leave the pin floating. These settings supports DDR3LV, DDR4, and DDR4LV supply voltages without an EEPROM change.

• The buck converters have an active discharge function. The discharge function can be disabled individually per rail in the DISCHARGE_CONFIG register. If discharge is enabled, the device discharges the output is discharged to ground whenever a rail is disabled.
• Prior to a sequence into ACTIVE state (from INITIALIZE or STBY state), the device discharges the disabled rails regardless of the discharge-configuration to avoid starting into a pre-biased output.
• If a rail is enabled by an I2C-command, active discharge is not enforced, but the rail is only enabled if the output voltage is below the SCG-threshold.
• This register is not EEPROM-backed and does reset if the device enters OFF-state.
• When in INITIALIZE state (during RESET or an I2C-OFF-request), the discharge configuration is not reset. Note: the power-down-sequence can be violated if the discharge function is disabled.

All Buck Converters support Dynamic Voltage Frequency Scaling (DVFS). The output-voltage can be changed during the operation to optimize the operating voltage for the operation point of the SoC in the lower output voltage range between 0.6 V and 1.4 V. The voltage change is controlled by writing to BUCK1_VOUT respectively BUCK2_VOUT or BUCK3_VOUT registers. During a DVFS-induced voltage transition, the active discharge function is temporarily enabled, irrespective of the discharge-configuration.

Output Capacitance Requirements

• for fixed-frequency, low-bandwidth configuration, a minimum capacitance of 12uF is required and a maximum total capacitance of 36uF is supported
• for quasi-fixed-frequency, low-bandwidth configuration, a minimum capacitance of 10uF is required and a maximum total capacitance of 75uF is supported
• for fixed-frequency, high-bandwidth configuration, a minimum capacitance of 48uF is required and a maximum total capacitance of 144uF is supported
• for quasi-fixed-frequency, high-bandwidth configuration, a minimum capacitance of 30uF is required and a maximum total capacitance of 220uF is supported

Buck Fault Handling

• The TPS65219-Q1 detects under voltages on the buck converter outputs. The reaction to the detection of an under-voltage is dependent on the configuration of the respective BUCKx_UV bit and the MASK_EFFECT bit in INT_MASK_BUCKS. If not masked, the device sets bit INT_BUCK_1_2_IS_SET respectively INT_BUCK_3_IS_SET bit in INT_SOURCE register and bit BUCKx_UV in INT_BUCK_1_2 respectively INT_BUCK_3 register.

  During a voltage transition (for example, when triggered by a DVFS induced voltage change), the device blanks the undervoltage detection by default and activates the undervoltage detection when the voltage transition completed.

  If the device detects an undervoltage during the sequence into ACTIVE state (from INITIALIZE or STBY) and UV is not masked, the power-down-sequence starts at the end of the current slot.

  If the device detects an undervoltage in ACTIVE-state or STBY-state and UV is not masked, the power-down sequence starts immediately. OC-detection is not maskable.
  

• The TPS65219-Q1 provides cycle-by-cycle current-limit on the buck converter outputs. If the device detects over-current for t_{DEGLITCH_OC_short}, respectively for t_{DEGLITCH_OC_long} (configurable individually per rail with EN_LONG_DEGL_FOR_OC_BUCKx in OC_DEGL_CONFIG register; applicable for rising-edge only), the device sets INT_BUCK_1_2_IS_SET respectively INT_BUCK_3_IS_SET bit in INT_SOURCE register and bit BUCKx_OC (for positive over-current) respectively BUCKx_NEG_OC (for negative over-current) in INT_BUCK_1_2 respectively INT_BUCK_3 register.

  During a voltage transition (for example, when triggered by a DVFS induced voltage change), the over current detection is blanked and only gets activated when the voltage transition is completed.

  If the over-current occurs during the sequence into ACTIVE state (from INITIALIZE or STBY), the device disables the affected rail immediately and starts the power-down-sequence at the end of the current slot.

  If the over-current occurs in ACTIVE-state or STBY-state, the device disables the affected rail immediately and starts the power-down sequence.

  OC-detection is not maskable, but the deglitch-time is configurable. It is strongly recommended to use t_{DEGLITCH_OC_short}. Extended over-current can lead to increased aging or overshoot upon recovery.
  

• The TPS65219-Q1 detects short-to-ground (SCG) faults on the buck-outputs. The reaction to the detection of an SCG event is to set INT_BUCK_1_2_IS_SET respectively INT_BUCK_3_IS_SET bit in INT_SOURCE register and bit BUCKx_SCG in INT_BUCK_1_2 respectively INT_BUCK_3 register. The affected rail is disabled immediately. The device sequences down all outputs and transitions into the INITIALIZE state.

  SCG-detection is not maskable.

  If a rail gets enabled, the device blanks SCG detection initially to allow the rail to ramp above the SCG-threshold.
  

• The TPS65219-Q1 detects residual voltage (RV) faults on the buck-outputs. The reaction to the detection of an RV event is to set INT_RV_IS_SET bit in INT_SOURCE register and bit BUCKx_RV in INT_RV register. The RV-detection is not maskable, but the nINT-reaction can be configured globally for all rails by MASK_INT_FOR_RV in INT_MASK_WARM register. The BUCKx_RV-flag is set regardless of masking, INT_RV_IS_SET bit is only set if nINT is asserted. The fault-reaction time and potential state-transition depends on the situation when residual voltage is detected:
  • If the device detects residual voltage during an ON-request in the INITIALIZE state, the device gates power-up and the device remains in INITIALIZE state. If the RV-condition exists for more than 4 ms to 5 ms, the device sets BUCKx_RV-bit. If the RV-condition is not present any more, the device transitions to ACTIVE state.
  • If the device detects residual voltage during power-up, ACTIVE_TO_STANDBY, or STANDBY_TO_ACTIVE sequences, the sequence is aborted and the device powers down.
  • If the device detects residual voltage for more than 80 ms on any rail that was disabled during STBY state during a request to leave STBY state, the device transitions into INITIALIZE state. The device sets the BUCKx_RV-bit if the condition persists for 4 ms to 5 ms, but less than 80 ms.
  • If the device detects residual voltage during power-up, ACTIVE_TO_STANDBY, or STANDBY_TO_ACTIVE sequences, the sequence is aborted and the device powers down.
  • If residual voltage is detected during an EN-command of the rail by I2C, the BUCKx_RV-flag is set immediately, but no state transition occurs.
• The buck converters have a local over-temperature sensor. The reaction to a temperature warning is dependent on the configuration of the respective SENSOR_x_WARM_MASK bit in MASK_CONFIG register and the MASK_EFFECT bits in INT_MASK_BUCKS register. If the temperature at the sensor exceeds T_{WARM_Rising} and is not masked, the device sets INT_SYSTEM_IS_SET bit in INT_SOURCE register and SENSOR_x_WARM bit in INT_SYSTEM register. In case the sensor detects a temperature exceeding T_{HOT_Rising} , the converters power dissipation and junction temperature exceeds safe operating value. The device powers down all active outputs immediately and sets INT_SYSTEM_IS_SET bit in INT_SOURCE register and SENSOR_x_HOT bit in INT_SYSTEM register. The TPS65219-Q1 automatically recovers once the temperature drops below the T_{WARM_Falling} threshold value (or below the T_{HOT_Falling} threshold value in case T_WARM is masked). The _HOT bit remains set and needs to be cleared by writing '1'. The HOT-detection is not maskable.