JAJSCX2F january 2017 – may 2023 TPS65235-1
PRODUCTION DATA
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TONEAMP | TIMER | ISW | FSET | EN | DOUTMODE | TONE_AUTO | TONE_TRANS |
R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-1b | R/W-0b | R/W-0b | R/W-1b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | TONEAMP | R/W | 0b | 0b = 22-kHz tone amplitude is 650 mV (typ) 1b = 22-kHz tone amplitude is 750 mV (typ) |
6 | TIMER | R/W | 0b | 0b = Hiccup ON time set to 4 ms and OFF time set to 128 ms 1b = Hiccup ON time set to 8 ms and OFF time set to 256 ms |
5 | ISW | R/W | 0b | 0b = Boost switch peak current limit set to 3 × IOCP + 0.8 A 1b = Boost switch peak current limit set to 5 × IOCP + 0.8 A |
4 | FSET | R/W | 0b | 0b = 1-MHz switching frequency 1b = 500-kHz switching frequency |
3 | EN | R/W | 1b | 0b = LNB output disabled 1b = LNB output voltage Enabled |
2 | DOUTMODE | R/W | 0b | 0b = DOUT is kept to low when DIN has the tone input 1b = Reserved, cannot set to 1b |
1 | TONE_AUTO | R/W | 0b | 0b = GDR (External bypass FET control) is controlled by TONE_TRANS 1b = GDR (External bypass FET control) is automatically controlled by 22-kHz tones transmit |
0 | TONE_TRANS | R/W | 1b | 0b = GDR output with VLNB voltage for tone receive. Bypass FET is OFF for tone receiving from satellite 1b = GDR output with VCP voltage. Bypass FET is ON for tone transmit from TPS65235-1 |
TONE_AUTO | TONE_TRANS | BYPASS FET |
---|---|---|
0b | 0b | OFF |
0b | 1b | ON |
1b | x | Auto Detect |
The TPS65235-1 has full range of diagnostic flags for operation and debug. Processor can read the status register to check the error conditions. After the error happens, the flags are changed, once the errors are gone, the flags are set back without I2C access.
If the TSD and OCP flags are triggered, FAULT pin will be pulled low, so FAULT pin can be the interrupt signal to processor. After TSD and OCP are set to 1b, the FAULT pin logic is latched to low, processor must read this status register to release the fault conditions.