JAJSCX2F january   2017  – may 2023 TPS65235-1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Boost Converter
      2. 7.3.2  Linear Regulator and Current Limit
      3. 7.3.3  Boost Converter Current Limit
      4. 7.3.4  Charge Pump
      5. 7.3.5  Slew Rate Control
      6. 7.3.6  Short-Circuit Protection, Hiccup, and Overtemperature Protection
      7. 7.3.7  Tone Generation
      8. 7.3.8  Tone Detection
      9. 7.3.9  Audio Noise Rejection
      10. 7.3.10 Disable and Enable
      11. 7.3.11 Component Selection
        1. 7.3.11.1 Boost Inductor
        2. 7.3.11.2 Capacitor Selection
        3. 7.3.11.3 Surge Components
        4. 7.3.11.4 Consideration for Boost Filtering and LNB Noise
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 Serial Interface Description
      2. 7.5.2 TPS65235-1 I2C Update Sequence
    6. 7.6 Register Maps
      1. 7.6.1 Control Register 1 (address = 0x00) [reset = 0x08]
      2. 7.6.2 Control Register 2 (address = 0x01) [reset = 0x09]
      3. 7.6.3 Status Register (address = 0x02) [reset = 0x29]
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 DiSEqc1.x Support
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 DiSEqc2.x Support
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 サード・パーティ製品に関する免責事項
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

–40°C ≤ TJ ≤ 125°C, VIN = 12 V, fSW = 1 MHz (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
INPUT SUPPLY
VINInput voltage range4.51220V
IDD(SDN)Shutdown supply currentEN = 0b90120150µA
ILDO(Q)LDO quiescent currentEN = 1b, IO = 0 A, VVLNB = 18.2 V1.558.5mA
UVLOVIN undervoltage lockoutVIN rising4.154.34.45V
Hysteresis280480550mV
OUTPUT VOLTAGE
VOUTRegulated output voltageV(ctrl) = 1, IO = 500 mA1818.218.4V
V(ctrl) = 0, IO = 500 mA13.2513.413.55V
SCL = 1b, V(ctrl) = 1, IO = 500 mA (Non I2C)19.1819.419.62V
SCL = 1b, V(ctrl) = 0, IO = 500 mA (Non I2C)14.4414.614.76V
I(OCP)Output short circuit current limitR(SET) = 200 kΩ, Full temperature580650720mA
TJ = 25°C629650688mA
fSWBoost switching frequencyf = 1 MHz97710601134kHz
I(limitsw)(1)Switching current limitVIN = 12 V, VOUT = 18.2 V, R(SET) = 200 kΩ3A
Rds(on)_LSOn resistance of low side FETVIN = 12 V90140210mΩ
V(drop)Linear regulator voltage dropoutIO = 500 mA, TONEAMP = 0b0.440.81.15V
IO = 500 mA, TONEAMP = 1b0.550.91.2V
I(cable)Cable good detection current thresholdVIN = 12 V, VOUT = 13.4 V or 18.2 V0.958.8mA
I(rev)Reverse bias currentEN = 1b, VVLNB = 21 V495865mA
I(rev_dis)Disabled reverse bias currentEN = 0b, VVLNB = 21 V2.94.66.3mA
LOGIC SIGNALS
Enable threshold (V(EN)), high1.6V
Enable threshold (V(EN)), low0.8V
I(EN)Enable internal pullup currentV(EN) = 1.5 V567µA
V(EN) = 1 V234µA
V(VCTRL_H)VCTRL logic threshold level for high-level input voltage2V
V(VCTRL_L)VCTRL logic threshold level for low-level input voltage0.8V
V(EXTM_H)EXTM logic threshold level for high-level input voltage2V
V(EXTM_L)EXTM logic threshold level for low-level input voltage0.8V
VOL(FAULT)FAULT output low voltageFAULT open drain, IOL = 1 mA0.4V
TONE
f(tone)Tone frequency22-kHz tone output202224kHz
A(tone)Tone amplitude0 mA ≤ IO ≤ 500 mA, CO = 100 nF, TONEAMP = 0b617650696mV
0 mA ≤ IO ≤ 500 mA, CO = 100 nF, TONEAMP = 1b703750803mV
D(tone)Tone duty cycle45%50%55%
f(EXTM)External tone input frequency range22-kHz tone output17.62226.4kHz
44-kHz tone output35.24452.8kHz
TONE DETECTION
f(DIN)Tone detector frequency capture range0.4-VPP sine wave17.62226.4kHz
V(DIN)Tone detector input amplitudeSine wave, 22 kHz0.31.5V
V(DOUT)DOUT output voltageTone present, Iload = 2 mA0.4V
GDRBypass FET gate voltage, LNBTONE_TRANS = 1b, V(LNB) = 18.2 V23.1123.524.33V
TONE_TRANS = 0b, V(LNB) = 18.2 V18.1718.218.23V
THERMAL SHUT-DOWN (JUNCTION TEMPERATURE)
T(TRIP)Thermal protection trip pointTemperature rising160°C
T(HYST)Thermal protection hysteresis20°C
I2C READ BACK FAULT STATUS
V(PGOOD)PGOOD trip levelsFeedback voltage UVP low94%96%97.1%
Feedback voltage UVP high93%94.5%95.5%
Feedback voltage OVP high104%106.6%108%
Feedback voltage OVP low102%104.6%106%
T(warn)Temperature warning threshold125°C
I2C INTERFACE
VIHSDA,SCL input high voltage2V
VILSDA,SCL input low voltage0.8V
IIInput currentSDA, SCL, 0.4 V ≤ VI ≤ 4.5 V–1010µA
VOLSDA output low voltageSDA open drain, IOL = 2 mA0.4V
f(SCL)Maximum SCL clock frequency400kHz
(1) Specified by design