JAJSCX2F january   2017  – may 2023 TPS65235-1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Boost Converter
      2. 7.3.2  Linear Regulator and Current Limit
      3. 7.3.3  Boost Converter Current Limit
      4. 7.3.4  Charge Pump
      5. 7.3.5  Slew Rate Control
      6. 7.3.6  Short-Circuit Protection, Hiccup, and Overtemperature Protection
      7. 7.3.7  Tone Generation
      8. 7.3.8  Tone Detection
      9. 7.3.9  Audio Noise Rejection
      10. 7.3.10 Disable and Enable
      11. 7.3.11 Component Selection
        1. 7.3.11.1 Boost Inductor
        2. 7.3.11.2 Capacitor Selection
        3. 7.3.11.3 Surge Components
        4. 7.3.11.4 Consideration for Boost Filtering and LNB Noise
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 Serial Interface Description
      2. 7.5.2 TPS65235-1 I2C Update Sequence
    6. 7.6 Register Maps
      1. 7.6.1 Control Register 1 (address = 0x00) [reset = 0x08]
      2. 7.6.2 Control Register 2 (address = 0x01) [reset = 0x09]
      3. 7.6.3 Status Register (address = 0x02) [reset = 0x29]
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 DiSEqc1.x Support
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 DiSEqc2.x Support
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 サード・パーティ製品に関する免責事項
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.6 Timing Requirements

MINNOMMAXUNIT
OUTPUT VOLTAGE
tr, tf13-V to 18-V transition rising falling timeC(TCAP) = 22 nF2ms
tON(min)Minimum on time for the Low side FET75102130ns
TONE
tr(tone)Tone rise time0 mA ≤ IO ≤ 500 mA, CO = 100 nF,
Control Reg1[0] = 0b		11µs
0 mA ≤ IO ≤ 500 mA, CO = 100 nF,
Control Reg1[0] = 1b, and EXTM has 44-kHz input		5.5µs
tf(tone)Tone fall time0 mA ≤ IO ≤ 500 mA, CO = 100 nF,
Control Reg1[0] = 0b		10.8µs
0 mA ≤ IO ≤ 500 mA, CO = 100 nF,
Control Reg1[0] = 1b, and EXTM has 44 kHz input		5.4µs
OVERCURRENT PROTECTION
tONOvercurrent protection ON timeTIMER = 0b2.33.755.52ms
tOFFOvercurrent protection OFF timeTIMER = 0b98.5118133.5ms
I2C INTERFACE
tBUFBus free time between a STOP and START condition1.3µs
tHD_STAHold time (repeated) START condition0.6µs
tSU_STOSetup time for STOP condition0.6µs
tLOWLOW period of the SCL clock1µs
tHIGHHIGH period of the SCL clock0.6µs
tSU_STASetup time for a repeated START condition0.6µs
tSU_DATData setup time0.1µs
tHD_DATData hold time00.9µs
tRCLRise time of SCL signalCapacitance of one bus line (pF)20 + 0.1 CB300ns
tRCL1Rise time of SCL Signal after a Repeated START condition and after an acknowledge BITCapacitance of one bus line (pF)20 + 0.1 CB300ns
tFCLFall time of SCL signalCapacitance of one bus line (pF)20 + 0.1 CB300ns
tRDARise time of SDA signalCapacitance of one bus line (pF)20 + 0.1 CB300ns
tFDAFall time of SDA signalCapacitance of one bus line (pF)20 + 0.1 CB300ns
CBCapacitance of one bus line(SCL and SDA)400pF