JAJSCX2F january   2017  – may 2023 TPS65235-1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Boost Converter
      2. 7.3.2  Linear Regulator and Current Limit
      3. 7.3.3  Boost Converter Current Limit
      4. 7.3.4  Charge Pump
      5. 7.3.5  Slew Rate Control
      6. 7.3.6  Short-Circuit Protection, Hiccup, and Overtemperature Protection
      7. 7.3.7  Tone Generation
      8. 7.3.8  Tone Detection
      9. 7.3.9  Audio Noise Rejection
      10. 7.3.10 Disable and Enable
      11. 7.3.11 Component Selection
        1. 7.3.11.1 Boost Inductor
        2. 7.3.11.2 Capacitor Selection
        3. 7.3.11.3 Surge Components
        4. 7.3.11.4 Consideration for Boost Filtering and LNB Noise
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 Serial Interface Description
      2. 7.5.2 TPS65235-1 I2C Update Sequence
    6. 7.6 Register Maps
      1. 7.6.1 Control Register 1 (address = 0x00) [reset = 0x08]
      2. 7.6.2 Control Register 2 (address = 0x01) [reset = 0x09]
      3. 7.6.3 Status Register (address = 0x02) [reset = 0x29]
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 DiSEqc1.x Support
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 DiSEqc2.x Support
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 サード・パーティ製品に関する免責事項
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

GUID-1C4A3D76-9DBF-480E-9597-0858836D7B68-low.svgFigure 5-1 RUK Package20-Pin WQFN With Exposed Thermal PadTop View
Table 5-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NO. NAME
1 LX I Switching node of the boost converter
2 VIN S Input of internal linear regulator
3 VCC O Internal 6.3-V power supply. Connect a 1-μF ceramic capacitor from this pin to ground. When VIN is 5 V, connect the VCC pin to the VIN pin.
4 AGND S Analog ground. Connect all ground pins and power pad together.
5 TCAP O Connect a capacitor to this pin to set the rise time of the LNB output.
6 ISET O Connect a resistor to this pin to set the LNB output current limit.
7 EN I Enable this pin to enable the VLNB output. pull this pin to ground to disable the output. The output is then pulled to ground, and, when the EN pin is low, the I2C interface can be accessed.
8 FAULT O Open drain output pin, it goes low if any fault flag is set.
9 ADDR I Connect a different resistor to this pin to set different I2C addresses (see the Table 7-4 table).
10 VCTRL I Voltage level at this pin to set the output voltage (see the Table 7-3).
11 SDA I/O I2C compatible bidirectional data
12 SCL I I2C compatible clock input
13 EXTM I External modulation logic input pin that activates the 22-kHz tone output. The feeding signal can be 22-kHz tone or logic high or low.
14 DOUT O Tone detection output
15 DIN I Tone detection input
16 VLNB O Output of the power supply connected to satellite receiver or switch
17 VCP O Gate drive supply voltage and output of charge pump. Connect a capacitor between this pin and the VLNB pin.
18 BOOST O Output of the boost regulator and Input voltage of the internal linear regulator
19 GDR O Control the gate of the external MOSFET for DiSEqc 2.x support
20 PGND S Power ground for the boost converter
— Thermal Pad — The thermal pad must be soldered to the printed circuit board (PCB) for optimal thermal performance. Use thermal vias on the PCB to enhance power dissipation.
(1) I = input, O = output, I/O = input and output, S = power supply