JAJSCX2F january   2017  – may 2023 TPS65235-1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Boost Converter
      2. 7.3.2  Linear Regulator and Current Limit
      3. 7.3.3  Boost Converter Current Limit
      4. 7.3.4  Charge Pump
      5. 7.3.5  Slew Rate Control
      6. 7.3.6  Short-Circuit Protection, Hiccup, and Overtemperature Protection
      7. 7.3.7  Tone Generation
      8. 7.3.8  Tone Detection
      9. 7.3.9  Audio Noise Rejection
      10. 7.3.10 Disable and Enable
      11. 7.3.11 Component Selection
        1. 7.3.11.1 Boost Inductor
        2. 7.3.11.2 Capacitor Selection
        3. 7.3.11.3 Surge Components
        4. 7.3.11.4 Consideration for Boost Filtering and LNB Noise
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 Serial Interface Description
      2. 7.5.2 TPS65235-1 I2C Update Sequence
    6. 7.6 Register Maps
      1. 7.6.1 Control Register 1 (address = 0x00) [reset = 0x08]
      2. 7.6.2 Control Register 2 (address = 0x01) [reset = 0x09]
      3. 7.6.3 Status Register (address = 0x02) [reset = 0x29]
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 DiSEqc1.x Support
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 DiSEqc2.x Support
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 サード・パーティ製品に関する免責事項
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.11.2 Capacitor Selection

The TPS65235-1 device has a 1-MHz nonsynchronous boost converter integrated and the boost converter features the internal compensation network. The TPS65235-1 device works well with both ceramic capacitor and electrolytic capacitor.

The recommended ceramic capacitors for the TPS65235-1 application are, at the minimum, rated as X7R/X5R, with a 35-V rating, and a 1206 size for the achieving lower LNB output ripple. Table 7-1 lists the recommended ceramic capacitors list for both 4.7-µH and 10-µH boost inductors.

If more cost-effictive design is needed, use a 100-µF electrolytic (low ESR) and a 10-µF or 35-V ceramic capacitor.

Table 7-1 Boost Inductor and Capacitor Selections
BOOST INDUCTORCAPACITORSTOLERANCE (%)RATING (V)SIZE
10 µH2 × 22 µF±10351206
2 × 10 µF±10351206
4.7 µH2 × 22 µF±10351206
2 × 10 µF±10351206
22 µF±10351206

Figure 7-6 and Figure 7-7 show a bode plot of boost loop with 4.7-µH and 10-µH inductance and 4 µF, 5 µF, 7.5 µF, 10 µF, 15 µF, and 20 µF of boost capacitance after degrading. As the boost capacitance increases, the phase margin increases.

GUID-F8AD8767-B462-4DBA-8345-5C6FFD2A8B2A-low.gifFigure 7-6 Gain and Phase Margin of the Boost Loop With Different Boost Capacitance (VIN = 12 V, VOUT = 18.2 V, ILOAD = 1 A, fSW = 1 MHz, 4.7 µH, Typical Bode Plot)
GUID-FC56A8EB-9229-422B-9565-F43AAE988877-low.gifFigure 7-7 Gain and Phase Margin of the Boost Loop With Different Boost Capacitance (VIN = 12 V, VOUT = 18.2 V, ILOAD = 1 A, fSW = 1 MHz, 10 µH, Typical Bode Plot)