JAJSI91D december   2019  – may 2023 TPS652353

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Boost Converter
      2. 7.3.2  Linear Regulator and Current Limit
      3. 7.3.3  Boost Converter Current Limit
      4. 7.3.4  Charge Pump
      5. 7.3.5  Slew Rate Control
      6. 7.3.6  Short Circuit Protection, Hiccup and Overtemperature Protection
      7. 7.3.7  Tone Generation
      8. 7.3.8  Tone Detection
      9. 7.3.9  Audio Noise Rejection
      10. 7.3.10 Disable and Enable
      11. 7.3.11 Component Selection
        1. 7.3.11.1 Boost Inductor
        2. 7.3.11.2 Capacitor Selection
        3. 7.3.11.3 Surge Components
        4. 7.3.11.4 Consideration for Boost Filtering and LNB Noise
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 Serial Interface Description
      2. 7.5.2 TPS652353 I2C Update Sequence
    6. 7.6 Register Maps
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 DiSEqc1.x Support
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 DiSEqc2.x Support
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 サード・パーティ製品に関する免責事項
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.6 Register Maps

Control Register 1 (address = 0x00) [reset = 0x08]

Figure 7-12 Control Register 1
7 6 5 4 3 2 1 0
I2C_CON PWM/PSM RESERVED VSET[3:0] EXTM TONE
R/W-0b R/W-0b R/W-0b R/W-0100b R/W-0b
Table 7-5 Control Register 1
Bit Field Type Reset Description
7 I2C_CON R/W 0b

0b = I2C control disabled

1b = I2C control enabled
6 PWM/PSM R/W 0b

0b = PSM at light load

1b = Forced PWM
5 RESERVED R/W 0b

Reserved
4-1 VSET[3:0] R/W 0100b

LNB output voltage selection

0000b = 11 V

0001b = 11.6 V

0010b = 12.2 V

0011b = 12.8 V

0100b = 13.4 V

0101b = 14 V

0110b = 14.6 V

0111b = 15.2 V

1000b = 15.8 V

1001b = 16.4 V

1010b = 17 V

1011b = 17.6 V

1100b = 18.2 V

1101b = 18.8 V

1110b = 19.4 V

1111b = 21 V
0 EXTM TONE R/W 0b

0b = EXTM 44-kHz tone input not support, with only 22-kHz tone output at VLNB

1b = EXTM 44-kHz tone input support, with 44-kHz tone output at VLNB

Control Register 2 (address = 0x01) [reset = 0x09]

Figure 7-13 Control Register 2
7 6 5 4 3 2 1 0
TONEAMP TIMER ISW FSET EN DOUTMODE TONE_AUTO TONE_TRANS
R/W-0b R/W-0b R/W-0b R/W-0b R/W-1b R/W-0b R/W-0b R/W-1b
Table 7-6 Control Register 2
Bit Field Type Reset Description
7 TONEAMP R/W 0b

0b = 22-kHz tone amplitude is 650 mV (typ)

1b = 22-kHz tone amplitude is 750 mV (typ)
6 TIMER R/W 0b

0b = Hiccup ON time set to 29 ms and OFF time set to 233 ms

1b = Hiccup ON time set to 58 ms and OFF time set to 466 ms

( If ISW is set as 1A, recommend to set TIMER as 0b. )
5 ISW R/W 0b

0b = Boost switch peak current limit set to 3 × IOCP + 0.8 A

1b = Boost switch peak current limit set to 5 × IOCP + 0.8 A
4 FSET R/W 0b

0b = 1-MHz switching frequency

1b = 500-kHz switching frequency
3 EN R/W 1b

0b = LNB output disabled

1b = LNB output voltage Enabled
2 DOUTMODE R/W 0b

0b = DOUT is kept to low when DIN has the tone input

1b = Reserved, cannot set to 1b
1 TONE_AUTO R/W 0b

0b = GDR (External bypass FET control) is controlled by TONE_TRANS

1b = GDR (External bypass FET control) is automatically controlled by 22-kHz tones transmit
0 TONE_TRANS R/W 1b

0b = GDR output with VLNB voltage for tone receive. Bypass FET is OFF for tone receiving from satellite

1b = GDR output with VCP voltage. Bypass FET is ON for tone transmit from TPS652353
Table 7-7 22-kHz Tone Receive Mode Selection
TONE_AUTO TONE_TRANS BYPASS FET
0b 0b OFF
0b 1b ON
1b x Auto Detect

The TPS652353 has full range of diagnostic flags for operation and debug. Processor can read the status register to check the error conditions. Once the error happens, the flags are changed, once the errors are gone, the flags are set back without I2C access.

If the TSD and OCP flags are triggered, FAULT pin will be pulled low, so FAULT pin can be the interrupt signal to processor. Once TSD and OCP are set to 1b, the FAULT pin logic is latched to low, processor need to read this status register to release the fault conditions.

Status Register (address = 0x02) [reset = 0x29]

Figure 7-14 Status Register
7 6 5 4 3 2 1 0
Reserved 0 LDO_ON T125 TSD OCP CABLE_GOOD VOUT_GOOD
R-0b R-0b R-0b R-0b R-1b R-0b R-0b R-1b
Table 7-8 Status Register
Bit Field Type Reset Description
7 Reserved R 0b

Reserved
6 TDETGOOD R 0b

0b = 22-kHz tone detected on DIN pin is out of range

1b = 22-kHz tone detected on DIN pin is in range
5 LDO_ON R 1b

0b = Internal LDO is turned off but boost converter is on

1b = Internal LDO is turned on and boost converter is on
4 T125 R 0b

0b = Die temperature < 125°C

1b = Die temperature > 125°C
3 TSD R 1b

0b = No thermal shutdown triggered

1b = Thermal shutdown triggered. The FAULT pin logic is latched to low, processor need to read this register to release the fault conditions
2 OCP R 0b

0b = Overcurrent protection conditions released

1b = Overcurrent protection triggered. The FAULT pin logic is latched to low, processor need to read this register to release the fault conditions
1 CABLE_GOOD R 0b

0b = Cable not connected

1b = Cable connection good
0 VOUT_GOOD R 1b

0b = LNB output voltage out of range

1b = LNB output voltage in range