JAJSI91D december   2019  – may 2023 TPS652353

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Boost Converter
      2. 7.3.2  Linear Regulator and Current Limit
      3. 7.3.3  Boost Converter Current Limit
      4. 7.3.4  Charge Pump
      5. 7.3.5  Slew Rate Control
      6. 7.3.6  Short Circuit Protection, Hiccup and Overtemperature Protection
      7. 7.3.7  Tone Generation
      8. 7.3.8  Tone Detection
      9. 7.3.9  Audio Noise Rejection
      10. 7.3.10 Disable and Enable
      11. 7.3.11 Component Selection
        1. 7.3.11.1 Boost Inductor
        2. 7.3.11.2 Capacitor Selection
        3. 7.3.11.3 Surge Components
        4. 7.3.11.4 Consideration for Boost Filtering and LNB Noise
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 Serial Interface Description
      2. 7.5.2 TPS652353 I2C Update Sequence
    6. 7.6 Register Maps
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 DiSEqc1.x Support
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 DiSEqc2.x Support
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 サード・パーティ製品に関する免責事項
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

–40°C ≤ TJ ≤ 125°C, VIN = 12 V, fSW = 1 MHz (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT SUPPLY
VIN Input voltage range 4.5 12 20 V
IDD(SDN) Shutdown supply current EN = 0b 90 120 150 µA
ILDO(Q) LDO quiescent current EN = 1b, IO = 0 A, VVLNB = 18.2 V 1.5 5 8.5 mA
UVLO VIN undervoltage lockout VIN rising 4.15 4.3 4.45 V
Hysteresis 280 480 550 mV
OUTPUT VOLTAGE
VOUT Regulated output voltage V(ctrl) = 1, IO = 500 mA 18 18.2 18.4 V
V(ctrl) = 0, IO = 500 mA 13.25 13.4 13.55 V
SCL = 1b, V(ctrl) = 1, IO = 500 mA (Non I2C) 19.18 19.4 19.62 V
SCL = 1b, V(ctrl) = 0, IO = 500 mA (Non I2C) 14.44 14.6 14.76 V
I(OCP) Output short circuit current limit R(SET) = 200 kΩ, Full temperature 580 650 720 mA
TJ = 25°C 629 650 688 mA
fSW Boost switching frequency f = 1 MHz 977 1060 1134 kHz
I(limitsw)(1) Switching current limit VIN = 12 V, VOUT = 18.2 V, R(SET) = 200 kΩ 3 A
Rds(on)_LS On resistance of low side FET VIN = 12 V 90 140 210 mΩ
V(drop) Linear regulator voltage dropout IO = 500 mA, TONEAMP = 0b 0.44 0.8 1.15 V
IO = 500 mA, TONEAMP = 1b 0.55 0.9 1.2 V
I(cable) Cable good detection current threshold VIN = 12 V, VOUT = 13.4 V or 18.2 V 0.9 5 8.8 mA
I(rev) Reverse bias current EN = 1b, VVLNB = 21 V 49 58 65 mA
I(rev_dis) Disabled reverse bias current EN = 0b, VVLNB = 21 V 2.9 4.6 6.3 mA
LOGIC SIGNALS
Enable threshold (V(EN)), high 1.6 V
Enable threshold (V(EN)), low 0.8 V
I(EN) Enable internal pullup current V(EN) = 1.5 V 5 6 7 µA
V(EN) = 1 V 2 3 4 µA
V(VCTRL_H) VCTRL logic threshold level for high-level input voltage 2 V
V(VCTRL_L) VCTRL logic threshold level for low-level input voltage 0.8 V
V(EXTM_H) EXTM logic threshold level for high-level input voltage 2 V
V(EXTM_L) EXTM logic threshold level for low-level input voltage 0.8 V
VOL(FAULT) FAULT output low voltage FAULT open drain, IOL = 1 mA 0.4 V
TONE
f(tone) Tone frequency 22-kHz tone output 20 22 24 kHz
A(tone) Tone amplitude 0 mA ≤ IO ≤ 500 mA, CO = 100 nF, TONEAMP = 0b 617 650 696 mV
0 mA ≤ IO ≤ 500 mA, CO = 100 nF, TONEAMP = 1b 703 750 803 mV
D(tone) Tone duty cycle 45% 50% 55%
f(EXTM) External tone input frequency range 22-kHz tone output 17.6 22 26.4 kHz
44-kHz tone output 35.2 44 52.8 kHz
TONE DETECTION
f(DIN) Tone detector frequency capture range 0.4-VPP sine wave 17.6 22 26.4 kHz
V(DIN) Tone detector input amplitude Sine wave, 22 kHz 0.3 1.5 V
V(DOUT) DOUT output voltage Tone present, Iload = 2 mA 0.4 V
GDR Bypass FET gate voltage, LNB TONE_TRANS = 1b, V(LNB) = 18.2 V 23.11 23.5 24.33 V
TONE_TRANS = 0b, V(LNB) = 18.2 V 18.17 18.2 18.23 V
THERMAL SHUT-DOWN (JUNCTION TEMPERATURE)
T(TRIP) Thermal protection trip point Temperature rising 160 °C
T(HYST) Thermal protection hysteresis 20 °C
I2C READ BACK FAULT STATUS
V(PGOOD) PGOOD trip levels Feedback voltage UVP low 94% 96% 97.1%
Feedback voltage UVP high 93% 94.5% 95.5%
Feedback voltage OVP high 104% 106.6% 108%
Feedback voltage OVP low 102% 104.6% 106%
T(warn) Temperature warning threshold 125 °C
I2C INTERFACE
VIH SDA,SCL input high voltage 2 V
VIL SDA,SCL input low voltage 0.8 V
II Input current SDA, SCL, 0.4 V ≤ VI ≤ 4.5 V –10 10 µA
VOL SDA output low voltage SDA open drain, IOL = 2 mA 0.4 V
f(SCL) Maximum SCL clock frequency 400 kHz
(1) Specified by design