JAJSC02C december   2013  – may 2023 TPS65261 , TPS65261-1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Adjusting the Output Voltage
      2. 7.3.2  Power Failure Detector
      3. 7.3.3  Enable and Adjusting Undervoltage Lockout
      4. 7.3.4  Soft-Start Time
      5. 7.3.5  Power Up Sequencing
        1. 7.3.5.1 External Power Sequencing
        2. 7.3.5.2 Automatic Power Sequencing
      6. 7.3.6  V7V Low Dropout Regulator and Bootstrap
      7. 7.3.7  Out-of-Phase Operation
      8. 7.3.8  Output Overvoltage Protection (OVP)
      9. 7.3.9  Slope Compensation
      10. 7.3.10 Overcurrent Protection
        1. 7.3.10.1 High-side MOSFET Overcurrent Protection
        2. 7.3.10.2 Low-side MOSFET Overcurrent Protection
      11. 7.3.11 Power Good
      12. 7.3.12 Adjustable Switching Frequency
      13. 7.3.13 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Pulse Skipping MODE (PSM)
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Output Inductor Selection
        2. 8.2.2.2 Output Capacitor Selection
        3. 8.2.2.3 Input Capacitor Selection
        4. 8.2.2.4 Loop Compensation
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Parts
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

GUID-BBF68A9B-BAD9-47FB-85F3-E4A16680C459-low.gif
(There is no electric signal down bonded to thermal pad inside IC. Exposed thermal pad must be soldered to PCB for optimal thermal performance.)
Figure 5-1 RHB Package 8-Pin VQFN (Top View)
Table 5-1 Pin Functions
PIN DESCRIPTION
NO. NAME
1 EN3 Enable for buck3. Float to enable. Can use this pin to adjust the input undervoltage lockout of buck3 with a resistor divider.
2 PGOOD An open drain output, asserts low if output voltage of any buck beyond regulation range due to thermal shutdown, overcurrent, undervoltage or ENx shut down.
3 RESET Open drain power failure output signal.
4 MODE When high, an automatic power-up/power-down sequence is provided according to states of EN1, EN2 and EN3 pins.
5 V7V Internal LDO for gate driver and internal controller. Connect a 10-µF capacitor from the pin to power ground
6 FB2 Feedback Kelvin sensing pin for buck2 output voltage. Connect this pin to buck2 resistor divider.
7 COMP2 Error amplifier output and Loop compensation pin for buck2. Connect a series resistor and capacitor to compensate the control loop of buck2 with peak current PWM mode.
8 SS2 Soft-start and tracking input for buck2. An internal 5-µA pullup current source is connected to this pin. The soft-start time can be programmed by connecting a capacitor between this pin and ground.
9 BST2 Boot strapped supply to the high side floating gate driver in buck2. Connect a capacitor (recommend 47nF) from BST2 pin to LX2 pin.
10 LX2 Switching node connection to the inductor and bootstrap capacitor for buck2. The voltage swing at this pin is from a diode voltage below the ground up to PVIN2 voltage.
11 PGND2 Power ground connection of buck2. Connect PGND2 pin as close as practical to the (–) terminal of VIN2 input ceramic capacitor.
12 PVIN2 Input power supply for buck2. Connect PVIN2 pin as close as practical to the (+) terminal of an input ceramic capacitor (suggest 10µF).
13 PVIN3 Input power supply for buck3. Connect PVIN3 pin as close as practical to the (+) terminal of an input ceramic capacitor (suggest 10µF).
14 PGND3 Power ground connection of buck3. Connect PGND3 pin as close as practical to the (–) terminal of VIN3 input ceramic capacitor.
15 LX3 Switching node connection to the inductor and bootstrap capacitor for buck3. The voltage swing at this pin is from a diode voltage below the ground up to PVIN3 voltage.
16 BST3 Boot strapped supply to the high side floating gate driver in buck3. Connect a capacitor (recommend 47nF) from BST3 pin to LX3 pin.
17 SS3 Soft-start and tracking input for buck3. An internal 5-µA pullup current source is connected to this pin. The soft-start time can be programmed by connecting a capacitor between this pin and ground.
18 COMP3 Error amplifier output and Loop compensation pin for buck3. Connect a series resistor and capacitor to compensate the control loop of buck3 with peak current PWM mode.
19 FB3 Feedback Kelvin sensing pin for buck3 output voltage. Connect this pin to buck3 resistor divider.
20 ROSC Oscillator frequency programmable pin. Connect an external resistor to set the switching frequency.
21 AGND Analog ground common to buck controllers and other analog circuits. It must be routed separately from high current power grounds to the (–) terminal of bypass capacitor of input voltage VIN.
22 FB1 Feedback Kelvin sensing pin for buck1 output voltage. Connect this pin to buck1 resistor divider.
23 COMP1 Error amplifier output and Loop compensation pin for buck1. Connect a series resistor and capacitor to compensate the control loop of buck1 with peak current PWM mode.
24 SS1 Soft-start and tracking input for buck1. An internal 5-µA pullup current source is connected to this pin. The soft-start time can be programmed by connecting a capacitor between this pin and ground.
25 BST1 Boot strapped supply to the high side floating gate driver in buck1. Connect a capacitor (recommend 47nF) from BST1 pin to LX1 pin.
26 LX1 Switching node connection to the inductor and bootstrap capacitor for buck1. The voltage swing at this pin is from a diode voltage below the ground up to PVIN1 voltage.
27 PGND1 Power ground connection of Buck1. Connect PGND1 pin as close as practical to the (–) terminal of VIN1 input ceramic capacitor.
28 PVIN1 Input power supply for buck1. Connect PVIN1 pin as close as practical to the (+) terminal of an input ceramic capacitor (suggest 10µF).
29 VIN Buck controller power supply.
30 VDIV Input voltage threshold for power failure detection of input voltage.
31 EN1 Enable for buck1. Float to enable. Can use this pin to adjust the input undervoltage lockout of buck1 with a resistor divider.
32 EN2 Enable for buck2. Float to enable. Can use this pin to adjust the input undervoltage lockout of buck2 with a resistor divider.
PAD There is no electric signal down bonded to thermal pad inside IC. Exposed thermal pad must be soldered to PCB for optimal thermal performance.