JAJSC02C december   2013  – may 2023 TPS65261 , TPS65261-1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Adjusting the Output Voltage
      2. 7.3.2  Power Failure Detector
      3. 7.3.3  Enable and Adjusting Undervoltage Lockout
      4. 7.3.4  Soft-Start Time
      5. 7.3.5  Power Up Sequencing
        1. 7.3.5.1 External Power Sequencing
        2. 7.3.5.2 Automatic Power Sequencing
      6. 7.3.6  V7V Low Dropout Regulator and Bootstrap
      7. 7.3.7  Out-of-Phase Operation
      8. 7.3.8  Output Overvoltage Protection (OVP)
      9. 7.3.9  Slope Compensation
      10. 7.3.10 Overcurrent Protection
        1. 7.3.10.1 High-side MOSFET Overcurrent Protection
        2. 7.3.10.2 Low-side MOSFET Overcurrent Protection
      11. 7.3.11 Power Good
      12. 7.3.12 Adjustable Switching Frequency
      13. 7.3.13 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Pulse Skipping MODE (PSM)
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Output Inductor Selection
        2. 8.2.2.2 Output Capacitor Selection
        3. 8.2.2.3 Input Capacitor Selection
        4. 8.2.2.4 Loop Compensation
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Parts
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.11 Power Good

The PGOOD pin is an open drain output. After feedback voltage of each buck is between 95% (rising) and 105% (falling) of the internal voltage reference, the PGOOD pin pull-down is de-asserted and the pin floats. It is recommended to use a pull-up resistor between the values of 10kΩ and 100kΩ to a voltage source that is 5.5V or less. The PGOOD is in a defined state after the VIN input voltage is greater than 1V, but with reduced current sinking capability. The PGOOD achieves full current sinking capability after the VIN input voltage is above UVLO threshold, which is 4.25V.

The PGOOD pin is pulled low when any feedback voltage of a buck is lower than 92.5% (falling) or greater than 107.5% (rising) of the nominal internal reference voltage. Also, the PGOOD is pulled low if the input voltage is undervoltage locked up, thermal shutdown is asserted, the EN pin is pulled low or the converter is in a soft-start period.