JAJSQ69B december   2015  – may 2023 TPS65265

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Adjusting the Output Voltage
      2. 8.3.2  Mix PGOOD, PG_DLY Functions
        1. 8.3.2.1 Programmable PGOOD DELAY
        2. 8.3.2.2 Relay Control
      3. 8.3.3  Enable and Adjusting UVLO
      4. 8.3.4  Soft-Start Time
      5. 8.3.5  Power-Up Sequencing
        1. 8.3.5.1 External Power Sequencing
        2. 8.3.5.2 Automatic Power Sequencing
      6. 8.3.6  V7V Low Dropout Regulator and Bootstrap
      7. 8.3.7  Out of Phase Operation
      8. 8.3.8  Output Overvoltage Protection (OVP)
      9. 8.3.9  PSM
      10. 8.3.10 Slope Compensation
      11. 8.3.11 Overcurrent Protection
        1. 8.3.11.1 High-Side MOSFET Overcurrent Protection
        2. 8.3.11.2 Low-Side MOSFET Overcurrent Protection
      12. 8.3.12 Adjustable Switching Frequency
      13. 8.3.13 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operation With VIN < 4 V (Minimum VIN)
      2. 8.4.2 Operation With EN Control
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Output Inductor Selection
        2. 9.2.2.2 Output Capacitor Selection
        3. 9.2.2.3 Input Capacitor Selection
        4. 9.2.2.4 Loop Compensation
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 ドキュメントの更新通知を受け取る方法
    2. 10.2 サポート・リソース
    3. 10.3 Trademarks
    4. 10.4 静電気放電に関する注意事項
    5. 10.5 用語集
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

GUID-C5000703-11F3-4A2B-9137-CABE6731EDBD-low.gif
There is no electric signal down bonded to thermal pad inside IC. Exposed thermal pad must be soldered to PCB for optimal thermal performance.
Figure 6-1 RHB Package32-Lead Plastic QFNTop View
Table 6-1 Pin Functions
PIN DESCRIPTION
NO. NAME
1 V7V Internal LDO for gate driver and internal controller. Connect a 10-µF capacitor from the pin to power ground
2 PGOOD An open drain output, asserts low if output voltage of any buck beyond regulation range due to thermal shutdown, over-current, under-voltage or ENx shut down.
3 EN1 Enable for buck1. Float to enable. Can use this pin to adjust the input undervoltage lockout (UVLO) of buck1 with a resistor divider.
4 EN2 Enable for buck2. Float to enable. Can use this pin to adjust the input UVLO of buck2 with a resistor divider.
5 EN3 Enable for buck3. Float to enable. Can use this pin to adjust the input UVLO of buck3 with a resistor divider.
6 FB2 Feedback Kelvin sensing pin for buck2 output voltage. Connect this pin to buck2 resistor divider.
7 COMP2 Error amplifier output and Loop compensation pin for buck2. Connect a series resistor and capacitor to compensate the control loop of buck2 with peak current PWM mode.
8 MODE When floating, Buck1/2/3 are controlled separate by EN1/2/3. When tied to HIGH or tied to GND, an automatic power-up/power-down sequence is provided according to states of EN1, EN2 and EN3 pins.
9 BST2 Boot strapped supply to the high side floating gate driver in buck2. Connect a capacitor (recommend 47nF) from BST2 pin to LX2 pin.
10 PGND2 Power ground connection of buck2. Connect PGND2 pin as close as practical to the (-) terminal of PVIN2 input ceramic capacitor.
11 LX2 Switching node connection to the inductor and bootstrap capacitor for buck2. The voltage swing at this pin is from a diode voltage below the ground up to PVIN2 voltage.
12 PVIN2 Input power supply for buck2. Connect PVIN2 pin as close as practical to the (+) terminal of an input ceramic capacitor (suggest 10 µF).
13 PVIN3 Input power supply for buck3. Connect PVIN3 pin as close as practical to the (+) terminal of an input ceramic capacitor (suggest 10 µF).
14 LX3 Switching node connection to the inductor and bootstrap capacitor for buck3. The voltage swing at this pin is from a diode voltage below the ground up to PVIN3 voltage.
15 PGND3 Power ground connection of buck3. Connect PGND3 pin as close as practical to the (-) terminal of PVIN3 input ceramic capacitor.
16 BST3 Boot strapped supply to the high side floating gate driver in buck3. Connect a capacitor (recommend 47nF) from BST3 pin to LX3 pin.
17 SEQ_DLY Delay time programmable between bucks at automatic power sequencing mode. Connect an external capacitor to set the interval delay time.
18 COMP3 Error amplifier output and Loop compensation pin for buck3. Connect a series resistor and capacitor to compensate the control loop of buck3 with peak current PWM mode.
19 FB3 Feedback Kelvin sensing pin for buck3 output voltage. Connect this pin to buck3 resistor divider.
20 ROSC Oscillator frequency programmable pin. Connect an external resistor to set the switching frequency.
21 AGND Analog ground common to buck controllers and other analog circuits.
22 FB1 Feedback Kelvin sensing pin for buck1 output voltage. Connect this pin to buck1 resistor divider.
23 COMP1 Error amplifier output and Loop compensation pin for buck1. Connect a series resistor and capacitor to compensate the control loop of buck1 with peak current PWM mode.
24 PG_DLY PGOOD delay programmable pin. Connect an external capacitor to set the delay time.
25 BST1 Boot strapped supply to the high side floating gate driver in buck1. Connect a capacitor (recommend 47nF) from BST1 pin to LX1 pin.
26, 27 PGND1 Power ground connection of Buck1. Connect PGND1 pin as close as practical to the (-) terminal of PVIN1 input ceramic capacitor.
28, 29 LX1 Switching node connection to the inductor and bootstrap capacitor for buck1. The voltage swing at this pin is from a diode voltage below the ground up to PVIN1 voltage.
30, 31 PVIN1 Input power supply for buck1. Connect PVIN1 pin as close as practical to the (+) terminal of an input ceramic capacitor (suggest 22 µF).
32 PSM Ties to HIGH or leaves floating, PSM mode; Ties to GND, FCCM mode.
PAD There is no electric signal down bonded to thermal pad inside IC. Exposed thermal pad must be soldered to PCB for optimal thermal performance.