JAJSQ69B december   2015  – may 2023 TPS65265

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Adjusting the Output Voltage
      2. 8.3.2  Mix PGOOD, PG_DLY Functions
        1. 8.3.2.1 Programmable PGOOD DELAY
        2. 8.3.2.2 Relay Control
      3. 8.3.3  Enable and Adjusting UVLO
      4. 8.3.4  Soft-Start Time
      5. 8.3.5  Power-Up Sequencing
        1. 8.3.5.1 External Power Sequencing
        2. 8.3.5.2 Automatic Power Sequencing
      6. 8.3.6  V7V Low Dropout Regulator and Bootstrap
      7. 8.3.7  Out of Phase Operation
      8. 8.3.8  Output Overvoltage Protection (OVP)
      9. 8.3.9  PSM
      10. 8.3.10 Slope Compensation
      11. 8.3.11 Overcurrent Protection
        1. 8.3.11.1 High-Side MOSFET Overcurrent Protection
        2. 8.3.11.2 Low-Side MOSFET Overcurrent Protection
      12. 8.3.12 Adjustable Switching Frequency
      13. 8.3.13 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operation With VIN < 4 V (Minimum VIN)
      2. 8.4.2 Operation With EN Control
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Output Inductor Selection
        2. 9.2.2.2 Output Capacitor Selection
        3. 9.2.2.3 Input Capacitor Selection
        4. 9.2.2.4 Loop Compensation
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 ドキュメントの更新通知を受け取る方法
    2. 10.2 サポート・リソース
    3. 10.3 Trademarks
    4. 10.4 静電気放電に関する注意事項
    5. 10.5 用語集
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.2.2.3 Input Capacitor Selection

The TPS65265 requires a high quality ceramic, type X5R or X7R, input decoupling capacitor of at least 10 µF of effective capacitance on the PVIN input voltage pins. In some applications additional bulk capacitance can also be required for the PVIN input. The effective capacitance includes any DC bias effects. The voltage rating of the input capacitor must be greater than the maximum input voltage. The capacitor must also have a ripple current rating greater than the maximum input current ripple of The TPS65265. The input ripple current can be calculated using Equation 17.

Equation 17. GUID-BA6A907F-BCF0-437E-B2CB-12C52D27B113-low.gif

The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to the capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors because they have a high capacitance to volume ratio and are fairly stable over temperature. The output capacitor must also be selected with the DC bias taken into account. The capacitance value of a capacitor decreases as the DC bias across a capacitor increases. The input capacitance value determines the input ripple voltage of the regulator. The input voltage ripple can be calculated using Equation 18.

Equation 18. GUID-776BA7BA-244E-4B0B-BE77-5945BE0FD112-low.gif