JAJSHI2E June   2014  – May 2019 TPS65283 , TPS65283-1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 代表的な回路図
    1.     効率、Vin = 12V、PSM
  5. 5 改訂履歴
  6. 6 概要（続き）
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 Handling Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Power Switch Detailed Description
        1. 9.3.1.1 Overcurrent Condition
        2. 9.3.1.2 Reverse Current and Voltage Protection
        3. 9.3.1.3 nFAULT Response
        4. 9.3.1.4 UVLO
        5. 9.3.1.5 Enable and Output Discharge
        6. 9.3.1.6 Power Switch Input and Output Capacitance
        7. 9.3.1.7 Programming the Current-Limit Threshold
      2. 9.3.2 Buck DC-DC Converter Detailed Description
        1. 9.3.2.1  Output Voltage
        2. 9.3.2.2  Adjustable Switching Frequency
        3. 9.3.2.3  Synchronization
        4. 9.3.2.4  Error Amplifier
        5. 9.3.2.5  Slope Compensation
        6. 9.3.2.6  Enable and Adjusting UVLO
        7. 9.3.2.7  Internal V7V Regulator
        8. 9.3.2.8  Short Circuit Protection
          1. 9.3.2.8.1 High-Side MOSFET Overcurrent Protection
          2. 9.3.2.8.2 Low-Side MOSFET Overcurrent Protection
        9. 9.3.2.9  Bootstrap Voltage (BST) and Low Dropout Operation
        10. 9.3.2.10 Output Overvoltage Protection (OVP)
        11. 9.3.2.11 Power Good
        12. 9.3.2.12 Power-Up Sequencing
        13. 9.3.2.13 Thermal Performance
    4. 9.4 Device Functional Modes
      1. 9.4.1 Operation With VIN < 4.5 V (Minimum VIN)
      2. 9.4.2 Operation With EN Control
      3. 9.4.3 Operation at Light Loads
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Output Voltage Setting
        2. 10.2.2.2 Bootstrap Capacitor Selection
        3. 10.2.2.3 Inductor Selection
        4. 10.2.2.4 Output Capacitor Selection
        5. 10.2.2.5 Input Capacitor Selection
        6. 10.2.2.6 Minimum Output Voltage
        7. 10.2.2.7 Compensation Component Selection
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 PCB Layout Recommendation
      2. 12.1.2 Power Dissipation and Junction Temperature
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 ドキュメントのサポート
      1. 13.1.1 関連リンク
    2. 13.2 商標
    3. 13.3 静電気放電に関する注意事項
    4. 13.4 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 改訂履歴

Changes from D Revision (August 2017) to E Revision

Changes from C Revision (August 2014) to D Revision

  • Changed 「特長」の箇条書き項目を「100mA～2.7A」から「最高 2.7A」にGo
  • Deleted 「概要」の 1 番目および 2 番目の段落でテキスト「標準値 100mA から約 2.7A まで」をGo
  • Changed "232 kΩ" to "80.6 kΩ" in the Description for RSET in the Pin Functions table. Go
  • Added IOS spec condition for RSET = 80.6 kΩ Go
  • Changed from "RSET is 9.1 kΩ ≤ RLIM ≤ 232 kΩ" to "RSET is 9.1 kΩ ≤ RLIM ≤ 80.6 kΩ" in the Programming the Current-Limit Threshold section.Go
  • Changed from "...adjustable 75 mA to 2.7 A" to "up to 2.7 mA..." in the Comments section of Table 2 (4 places). Go

Changes from B Revision (July 2014) to C Revision

  • Updated V7V and VSYNC_LO minimum in Electrical CharacteristicsGo
  • Updated transition voltage to lower than 0.4 V for clock signal amplitudeGo

Changes from A Revision (June 2014) to B Revision

  • デバイスのステータスを「量産データ」に変更Go

Changes from * Revision (June 2014) to A Revision

  • Changed Equation 3 From: ƒosc (kHz) = 41008 × R (kΩ)–0.979 To: ƒosc (kHz) = 47863 × R (kΩ)–0.988Go