JAJSHW9A September   2019  – October 2020 TPS65296

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 PWM Operation and D-CAP3 Control
      2. 7.3.2 Advanced Eco-mode Control
      3. 7.3.3 Soft Start and Prebiased Soft Start
      4. 7.3.4 Power Good
      5. 7.3.5 Overcurrent Protection and Undervoltage Protection
      6. 7.3.6 Overvoltage Protection
      7. 7.3.7 UVLO Protection
      8. 7.3.8 Output Voltage Discharge
      9. 7.3.9 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Light Load Operation for VDD1 Buck and VDD2 Buck
      2. 7.4.2 Output State Control
      3. 7.4.3 Output Sequence Control
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 External Component Selection
          1. 8.2.2.1.1 Inductor Selection
          2. 8.2.2.1.2 Output Capacitor Selection
          3. 8.2.2.1.3 Input Capacitor Selection
          4. 8.2.2.1.4 Bootstrap Capacitor and Resistor Selection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Support Resources
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

GUID-F5EAF42F-6D8F-4D5A-8071-16941F2898A2-low.gif Figure 5-1 18-Pin VQFN RJE Package (Top View)
Table 5-1 Pin Functions
PIN I/O DESCRIPTION
NAME NO.
VLDOIN 1 P Power supply input for VDDQ LDO. Connect VDD2 in typical application.
VDDQ 2 O VDDQ 1.5-A LDO output. It is recommended to connect to 10-μF or larger capacitance for stability.
AGND 3 G Signal ground
VDDQSNS 4 I VDDQ output voltage feedback
VDD2SNS 5 I VDD2 output voltage feedback
VDDQREF 6 O Internal reference for VDDQ. Recommend to connect to 0.22-μF or larger capacitance for stability.
PVIN 7 P Input power supply for VDD2 buck
PGOOD 8 O Power good signal open-drain output. PGOOD goes high when VDD1 and VDD2 output voltage are within the target range.
PGND 9 G Power ground for VDD2 buck
VDDQ_EN 10 I VDDQ_EN signal input for VDDQ LDO enable control. For detail control setup, refer to Table 7-1.
VDD_EN 11 I VDD_EN signal input for VDD1 buck and VDD2 buck enable control. For detail control setup, refer to Table 7-1.
VDD1SNS 12 I VDD1 output voltage feedback
VCC_5V 13 P Power supply for VDD1 and VDD2 buck converter control logic circuit
PVIN_VDD1 14 P Input power supply for VDD1 buck
SW_VDD1 15 O VDD1 switching node connection to the inductor and bootstrap capacitor
PGND_VDD1 16 G Power ground for VDD1 buck
SW 17 O VDD2 switching node connection to the inductor and bootstrap capacitor
BST 18 I High-side MOSFET gate driver bootstrap voltage input for VDD2 buck. Connect a capacitor between the BST pin and the SW pin.