JAJSNJ1 データシート

JAJSNJ1H May 2013 – December 2021 TPS65310A-Q1

PRODUCTION DATA

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

RVJ|56
- MPQF275D

サーマルパッド・メカニカル・データ

RVJ|56
- QFND385A

発注情報

8.4.1 RESET

RESN and PRESN are open drain outputs which are active if one or more of the conditions listed in Table 8-1 are valid. RESN active (low) is extended for t_RESNHOLD after a reset is triggered. RESN is the main processor reset and also asserts PRESN as a peripheral signal.

PRESN is latched and is released when window trigger mode of the watchdog is enabled (first rising edge at WD pin).

RESN and PRESN must keep the main processor and peripheral devices in a defined state during power up and power down in case of improper supply voltages or a critical failure condition. Therefore, for low supply voltages the topology of the reset outputs specify that RESN and PRESN are always held at a low level when RESN and PRESN are asserted, even if V_IN falls below V_POR or the device is in SHUTDOWN mode.

Figure 8-3 RESET Functionality

Table 8-1 RESET Conditions

RESET CONDITIONS
POR, Loss of LPM Clock, and Thermal Shutdown	The device reinitializes all registers with their default values. Error counter is cleared.
Voltage Monitor BUCK 1-3	Input voltage at V_MON1-3 pin out-of-bounds: V_VMON1-3 < V_{MONTH_L} or V_VMON1-3 > V_{MONTH_H}
Over Voltage LDO	V_sense4 > V_{MONTH_H}
Voltage Monitor VIO	Input voltage at VIO pin out-of-bounds: V_VIO < V_{VIOMON TH}
Loss of GND	Open at PGNDx or GND pin
OT BUCK1-3, VREG	Overtemperature on BUCK1–3 or VREG
WD_RESET	Watchdog window violation

Any reset event (without POR, thermal shutdown, or loss of LPM clock) increments the error counter (EC) by one. After a reset is consecutively triggered N_RES times, the device transfers to the LPM0 state, and the EC is reset to 0. The counter is decremented by one if an SPI LPM0_CMD is received. Alternatively, the device can be put in LOCK state once an SPI LOCK_CMD is received. Once the device is locked, it cannot be activated again by a wake condition. The reset counter and lock function avoid cyclic start-up and shut-down of the device in case of a persistent fault condition. The reset counter content is cleared with a POR condition, a thermal shutdown or a loss of LPM clock. Once the device is locked, a voltage below V_POR at the VIN pin or a thermal shutdown condition are the only ways to unlock the device.