JAJSNJ1H May 2013 – December 2021 TPS65310A-Q1
PRODUCTION DATA
Both regulators are synchronous converters operating with a fixed switching frequency ƒSW = 0.98 MHz. For each buck converter, the output voltage is programmable with external resistors. The synchronous operation mode improves the overall efficiency. BUCK3 switches in phase with BUCK1, and BUCK2 switches at a 216° shift to BUCK3 to minimize input current ripple.
Each buck converter can provide a maximum current of 2 A and is protected against short circuits to ground. In case of a short circuit to ground, the integrated cycle-by-cycle current limit turns off the high-side FET when its current reaches IHS-Limit and the low-side FET is turned on until the end of the given cycle. When the current limit is reached in the beginning of the cycle for five consecutive cycles, the pulse-width modulation (PWM) is forced low for eight cycles to prevent uncontrolled current build-up. In case the low-side current limit of ILS-Limit is reached, for example, due an output short to VSUP2/3, the low-side FET is turned off until the end of the cycle. If this is detected shortly after the high-low PWM transition (immediately after the low-side overcurrent comparator blanking time), both FETs are turned off for eight cycles.
The output voltages of BUCK2/3 regulators are monitored by a central independent voltage-monitoring circuit, which has an independent voltage-monitoring bandgap reference for safety reasons. In addition BUCK2 and BUCK3 are thermally protected with a dedicated temperature sensor.