JAJSNJ1H May   2013  – December 2021 TPS65310A-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 概要 (続き)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 SPI Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Buck Controller (Buck1)
        1. 8.3.1.1 Operating Modes
        2. 8.3.1.2 Normal Mode PWM Operation
      2. 8.3.2 Synchronous Buck Converters Buck2 And Buck3
      3. 8.3.3 BOOST Converter
      4. 8.3.4 Frequency-Hopping Spread Spectrum
      5. 8.3.5 Linear Regulator LDO
      6. 8.3.6 Gate Driver Supply
    4. 8.4 Device Functional Modes
      1. 8.4.1  RESET
      2. 8.4.2  Soft Start
      3. 8.4.3  INIT
      4. 8.4.4  TESTSTART
      5. 8.4.5  TESTSTOP
      6. 8.4.6  VTCHECK
      7. 8.4.7  RAMP
      8. 8.4.8  Power-Up Sequencing
      9. 8.4.9  Power-Down Sequencing
      10. 8.4.10 Active
      11. 8.4.11 ERROR
      12. 8.4.12 LOCKED
      13. 8.4.13 LPM0
      14. 8.4.14 Shutdown
        1. 8.4.14.1 Power-On Reset Flag
      15. 8.4.15 Wake Pin
      16. 8.4.16 IRQ Pin
      17. 8.4.17 VBAT Undervoltage Warning
      18. 8.4.18 VIN Over Or Undervoltage Protection
      19. 8.4.19 External Protection
      20. 8.4.20 Overtemperature Detection And Shutdown
      21. 8.4.21 Independent Voltage Monitoring
      22. 8.4.22 GND Loss Detection
      23. 8.4.23 Reference Voltage
      24. 8.4.24 Shutdown Comparator
      25. 8.4.25 LED And High-Side Switch Control
      26. 8.4.26 Window Watchdog
      27. 8.4.27 Timeout In Start-Up Modes
    5. 8.5 Programming
      1. 8.5.1 SPI
        1. 8.5.1.1 FSI Bit
    6. 8.6 Register Maps
      1. 8.6.1 Register Description
      2. 8.6.2 NOP0X00
        1. 8.6.2.1  SPI_SCK_FAIL 0x03
        2. 8.6.2.2  LPMO_CMD 0x11
        3. 8.6.2.3  LOCK_CMD 0x12
        4. 8.6.2.4  PWR_STAT 0x21
        5. 8.6.2.5  SYS_STAT 0x22
        6. 8.6.2.6  SPI_STAT 0x23
        7. 8.6.2.7  COMP_STAT 0x24
        8. 8.6.2.8  DEV_REV 0x2F
        9. 8.6.2.9  PWR_CONFIG 0x31
        10. 8.6.2.10 DEV_CONFIG 0x32
        11. 8.6.2.11 CLOCK_CONFIG 0x33
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Buck Controller 1
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Adjusting the Output Voltage for the BUCK1 Controller
          2. 9.2.1.2.2 Output Inductor, Sense Resistor and Capacitor Selection for the BUCK1 Controller
          3. 9.2.1.2.3 Compensation of the Buck Controller
          4. 9.2.1.2.4 Bootstrap Capacitor for the BUCK1 Controller
        3. 9.2.1.3 BUCK 1 Application Curve
      2. 9.2.2 Synchronous Buck Converters BUCK2 and BUCK3
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Adjusting the Output Voltage for the BUCK2 and BUCK3 Converter
          2. 9.2.2.2.2 Output Inductor Selection for the BUCK2 and BUCK3 Converter
          3. 9.2.2.2.3 Compensation of the BUCK2 and BUCK3 Converters
          4. 9.2.2.2.4 Bootstrap Capacitor for the BUCK2/3 Converters
        3. 9.2.2.3 Application Curves
      3. 9.2.3 BOOST Converter
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
          1. 9.2.3.2.1 Adjusting the Output Voltage for the Boost Converter
          2. 9.2.3.2.2 Output Inductor and Capacitor Selection for the BOOST Converter
          3. 9.2.3.2.3 Compensation of the BOOST Converter
          4. 9.2.3.2.4 Output Diode for the BOOST Converter
        3. 9.2.3.3 BOOST Converter Application Curves
      4. 9.2.4 Linear Regulator
        1. 9.2.4.1 Design Requirements
        2. 9.2.4.2 Detailed Design Procedure
          1. 9.2.4.2.1 Adjusting the Output Voltage for the Linear Regulator
          2. 9.2.4.2.2 Output Capacitance for the Linear Regulator
        3. 9.2.4.3 Linear Regulator Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Buck Controller
      2. 11.1.2 Buck Converter
      3. 11.1.3 Boost Converter
      4. 11.1.4 Linear Regulator
      5. 11.1.5 Other Considerations
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

GUID-DE2CC041-5C1E-4873-B960-6F76CD32DCAD-low.gif Figure 6-1 RVJ Package. 56-Pin VQFN With Exposed Thermal Pad. Top View.
Table 6-1 Pin Functions
PIN TYPE(1) PULLUP
PULLDOWN		 DESCRIPTION
NAME NO.
BOOT1 10 I — The capacitor on these pins acts as the voltage supply for the high-side MOSFET gate-drive circuitry.
BOOT2 29 I — The capacitor on these pins act as the voltage supply for the high-side MOSFET gate drive circuitry.
BOOT3 42 I — The capacitor on these pins act as the voltage supply for the BUCK3 high-side MOSFET gate drive circuitry.
COMP1 18 O — Error amplifier output for the switching controller. External compensation network is connected to this node.
COMP2 34 I — Compensation selection for the BUCK2 switching converter
COMP3 37 I — Compensation selection for the BUCK3 switching converter.
COMP5 20 O — Error amplifier output for the boost switching controller. External compensation network is connected to this node.
CSN 44 I Pullup SPI – Chip select
DVDD 55 O — Internal DVDD output for decoupling
EXTSUP 8 I — Optional LV input for gate driver supply
GL 13 O — Gate driver – low-side FET
GND 56 O — Analog GND, digital GND and substrate connection
GPFET 3 O — Gate driver external protection PMOS FET.
GU 11 O — Gate driver – high-side FET
HSCTRL 5 O — High-side gate driver output
HSPWM 49 I Pulldown High side and LED PWM input
HSSENSE 6 I — Sense input high side and LED
IRQ 28 OD — Low battery interrupt output in operating mode
LDO 51 O — Linear regulated output (connect a low ESR ceramic output capacitor to this terminal)
PGND1 14 O — Ground for low-side FET driver
PGND2 32 O — Power ground of synchronous converter BUCK2
PGND3 39 O — Power ground of synchronous converter BUCK3
PGND5 22 O — Power ground boost converter
PH1 12 O — Switching node - BUCK1 (floating ground for high-side FET driver)
PH2 31 O — Switching node BUCK2
PH3 40 O — Switching node BUCK3
PH5 23 O — Switching node boost
PRESN 26 OD — Peripherals reset
RESN 27 OD — System reset
S1 15 I — Differential current sense inputs for BUCK1, S2 pull-down only active in RAMP and ACTIVE state
S2 16 I Pulldown
SCK 46 I Pulldown SPI – Clock
SDI 45 I Pulldown SPI – controller out, peripheral in
SDO 47 O — SPI – controller in, peripheral out - push-pull output supplied by VIO
VBOOST 24 I — Booster output voltage
VIN 2 I — Unprotected supply input for the base functionality and band gap 1. Supplied blocks are: RESET, WD, wake, SPI, temp sensing, voltage monitoring and the logic block.
VINPROT 4 I — Main input supply pin (gate drivers and bandgap2)
VIO 48 I — Supply input for the digital interface to the MCU. Voltage on this input is monitored. If VIO falls below UV threshold a reset is generated and the part enters error mode.
VMON1 17 I — Input pin for the independent voltage monitor at BUCK1
VMON2 33 I — Input pin for the independent voltage monitor at BUCK2
VMON3 38 I — Input pin for the independent voltage monitor at BUCK3
VREF 53 O — Accurate reference voltage output for peripherals on the system (for example, ADC)
VREG 9 O — Internal regulator for gate driver supply (decoupling) and VREF
VSENSE1 19 I — Input for externally sensed voltage of the output using a resistor divider network from their respective output line to ground.
VSENSE2 35 I — Input for externally sensed voltage of the output using a resistor divider network from their respective output line to ground
VSENSE3 36 I — Input for externally sensed voltage of the output using a resistor divider network from their respective output line to ground
VSENSE4 52 I — Input for externally sensed voltage of the output using a resistor divider network from their respective output line to ground.
VSENSE5 21 I — Input for externally sensed voltage of the boost output using a resistor divider network from their respective output line to ground.
VSSENSE 1 I — Input to monitor the battery line for undervoltage conditions. UV is indicated by the IRQ pin.
VSUP2 30 I — Input voltage supply for switch mode regulator BUCK2
VSUP3 41 I — Input voltage supply for switch mode regulator BUCK3
VSUP4 50 I — Input voltage supply for linear regulator LDO
VT 54 I — Input pin for the comparator with shutdown functionality. This input can be used to sense an external NTC resistor to shutdown the IC in case the ambient temperature is too high or too low. Tie to GND if not in use.
VT_REF 25 O — Shutdown comparator reference output. Internally connected to DVDD, current-limited. When not in use can be connected to DVDD or left open.
WAKE 7 I Pulldown Wake up input
WD 43 I Pulldown Watchdog input pin. WD is the trigger input coming from the MCU.
(1) Description of pin type: I = Input; O = Output; OD = Open-drain output