JAJSNJ1H May   2013  – December 2021 TPS65310A-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 概要 (続き)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 SPI Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Buck Controller (Buck1)
        1. 8.3.1.1 Operating Modes
        2. 8.3.1.2 Normal Mode PWM Operation
      2. 8.3.2 Synchronous Buck Converters Buck2 And Buck3
      3. 8.3.3 BOOST Converter
      4. 8.3.4 Frequency-Hopping Spread Spectrum
      5. 8.3.5 Linear Regulator LDO
      6. 8.3.6 Gate Driver Supply
    4. 8.4 Device Functional Modes
      1. 8.4.1  RESET
      2. 8.4.2  Soft Start
      3. 8.4.3  INIT
      4. 8.4.4  TESTSTART
      5. 8.4.5  TESTSTOP
      6. 8.4.6  VTCHECK
      7. 8.4.7  RAMP
      8. 8.4.8  Power-Up Sequencing
      9. 8.4.9  Power-Down Sequencing
      10. 8.4.10 Active
      11. 8.4.11 ERROR
      12. 8.4.12 LOCKED
      13. 8.4.13 LPM0
      14. 8.4.14 Shutdown
        1. 8.4.14.1 Power-On Reset Flag
      15. 8.4.15 Wake Pin
      16. 8.4.16 IRQ Pin
      17. 8.4.17 VBAT Undervoltage Warning
      18. 8.4.18 VIN Over Or Undervoltage Protection
      19. 8.4.19 External Protection
      20. 8.4.20 Overtemperature Detection And Shutdown
      21. 8.4.21 Independent Voltage Monitoring
      22. 8.4.22 GND Loss Detection
      23. 8.4.23 Reference Voltage
      24. 8.4.24 Shutdown Comparator
      25. 8.4.25 LED And High-Side Switch Control
      26. 8.4.26 Window Watchdog
      27. 8.4.27 Timeout In Start-Up Modes
    5. 8.5 Programming
      1. 8.5.1 SPI
        1. 8.5.1.1 FSI Bit
    6. 8.6 Register Maps
      1. 8.6.1 Register Description
      2. 8.6.2 NOP0X00
        1. 8.6.2.1  SPI_SCK_FAIL 0x03
        2. 8.6.2.2  LPMO_CMD 0x11
        3. 8.6.2.3  LOCK_CMD 0x12
        4. 8.6.2.4  PWR_STAT 0x21
        5. 8.6.2.5  SYS_STAT 0x22
        6. 8.6.2.6  SPI_STAT 0x23
        7. 8.6.2.7  COMP_STAT 0x24
        8. 8.6.2.8  DEV_REV 0x2F
        9. 8.6.2.9  PWR_CONFIG 0x31
        10. 8.6.2.10 DEV_CONFIG 0x32
        11. 8.6.2.11 CLOCK_CONFIG 0x33
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Buck Controller 1
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Adjusting the Output Voltage for the BUCK1 Controller
          2. 9.2.1.2.2 Output Inductor, Sense Resistor and Capacitor Selection for the BUCK1 Controller
          3. 9.2.1.2.3 Compensation of the Buck Controller
          4. 9.2.1.2.4 Bootstrap Capacitor for the BUCK1 Controller
        3. 9.2.1.3 BUCK 1 Application Curve
      2. 9.2.2 Synchronous Buck Converters BUCK2 and BUCK3
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Adjusting the Output Voltage for the BUCK2 and BUCK3 Converter
          2. 9.2.2.2.2 Output Inductor Selection for the BUCK2 and BUCK3 Converter
          3. 9.2.2.2.3 Compensation of the BUCK2 and BUCK3 Converters
          4. 9.2.2.2.4 Bootstrap Capacitor for the BUCK2/3 Converters
        3. 9.2.2.3 Application Curves
      3. 9.2.3 BOOST Converter
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
          1. 9.2.3.2.1 Adjusting the Output Voltage for the Boost Converter
          2. 9.2.3.2.2 Output Inductor and Capacitor Selection for the BOOST Converter
          3. 9.2.3.2.3 Compensation of the BOOST Converter
          4. 9.2.3.2.4 Output Diode for the BOOST Converter
        3. 9.2.3.3 BOOST Converter Application Curves
      4. 9.2.4 Linear Regulator
        1. 9.2.4.1 Design Requirements
        2. 9.2.4.2 Detailed Design Procedure
          1. 9.2.4.2.1 Adjusting the Output Voltage for the Linear Regulator
          2. 9.2.4.2.2 Output Capacitance for the Linear Regulator
        3. 9.2.4.3 Linear Regulator Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Buck Controller
      2. 11.1.2 Buck Converter
      3. 11.1.3 Boost Converter
      4. 11.1.4 Linear Regulator
      5. 11.1.5 Other Considerations
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics

VIN = VINPROT 4.8 V to 40 V, VSUPx = 3 V to 5.5 V, EXTSUP = 0 V, TJ = –40°C to +150°C, unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT VOLTAGE-CURRENT CONSUMPTION
VIN Device operating range Buck regulator operating range, Voltage on VIN and VINPROT pins 4 50 V
VPOR Power-on reset threshold Falling VIN 3.5 3.6 3.8 V
Rising VIN 3.9 4.2 4.3
VPOR_hyst Power-on reset hysteresis on VIN 0.47 0.6 0.73 V
ILPM0 LPM0 current consumption(1) TA = 25°C, All off, wake active, VIN = 13 V, Total current into VSSENSE, VIN and VINPROT 44 μA
ILPM0 LPM0 current (commercial vehicle application) consumption(1) TA = 130°C, All off, wake active, VIN = 24.5 V, Total current into VSSENSE, VIN and VINPROT 60 μA
IACTIVE1 ACTIVE total current consumption(2) BUCK1 = on, VIN = 13 V, EXTSUP = 0 V,
Qg of BUCK1 FETs = 15 nC, TA = 25°C, Total current into VSSENSE, VIN and VINPROT		 32 mA
IACTIVE123 BUCK1/2/3 = on, VIN = 13 V,
Qg of BUCK1 FETs = 15 nC, TA = 25°C, Total current into VSSENSE, VIN and VINPROT		 40 mA
IACTIVE1235 BUCK1/2/3, LDO, BOOST, high-side switch = on, VIN = 13 V,
Qg of BUCK1 FETs = 15 nC, TA = 25°C, EXTSUP = 5 V from BOOST, Total current into VSSENSE, VIN and VINPROT		 31 mA
IACTIVE1235_noEXT BUCK1/2/3, LDO, BOOST, high-side switch = on, VIN = 13 V,
Qg of BUCK1 FETs = 15 nC, TA = 25°C, EXTSUP = open, Total current into VSENSE, VIN and VINPROT		 53 mA
BUCK CONTROLLER (BUCK1)
VBUCK1 Adjustable output voltage range 3 11 V
VSense1_NRM Internal reference voltage in operating mode VSENSE1 pin, load = 0 mA, Internal REF = 0.8 V –1% 1%
VS1-2 VS1-2 for forward OC in CCM Maximum sense voltage VSENSE1 = 0.75 V (low duty cycle) 60 75 90 mV
Minimum sense voltage VSENSE 1 = 1 V (negative current limit) –65 –37.5 –23
ACS Current-sense voltage gain ∆VCOMP1 / ∆ (VS1 - VS2) 4 8 12
tOCBUCK1_BLK RSTN and ERROR mode transition, when overcurrent is detected for > tOCBUCK1_BLK 1 ms
tDEAD_BUCK1 Shoot-through delay, blanking time 25 ns
ƒSWBUCK1 Switching frequency fOSC / 10 MHz
DC Duty cycle High-side minimum on time 100 ns
Maximum duty cycle 98.75%
EXTERNAL NMOS GATE DRIVERS FOR BUCK CONTROLLER
IGpeak Gate driver peak current VREG = 5.8 V 0.6 A
RDSON_DRIVER Source and sink driver IG current for external MOSFET = 200 mA, VREG = 5.8 V,
VBOOT1-PH1 = 5.8 V		 5 10 Ω
VDIO1 Bootstrap diode forward voltage IBOOT1 = –200 mA, VREG-BOOT1 0.8 1.1 V
ERROR AMPLIFIER (OTA) FOR BUCK CONTROLLERS AND BOOST CONVERTER
gmEA Forward transconductance COMP1/2/3/5 = 0.8 V; source and sink = 5 µA, test in feedback loop 0.9 m℧
AEA Error amplifier DC gain 60 dB
SYNCHRONOUS BUCK CONVERTER BUCK2/3
VSUP2/3 Supply voltage 3 11 V
VBUCK2/3 Regulated output voltage range Iload = 0 to 2 A, VSUPx = VBUCK2/3 + Iload × 0.2 Ω 0.8 5.5 V
RDSON-HS RDSON high-side switch VBOOTx –PHx = 5.8 V 0.20 Ω
RDSON-LS RDSON low-side switch VREG = 5.8 V 0.20 Ω
IHS-Limit High-side switch current limit Static current limit test. In application L > 1 µH at IHS-Limit and ILS-Limit to limit dI / dt 2.4 2.9 3.5 A
ILS-Limit Low-side switch current limit Static current limit test. In application L > 1 µH at IHS-Limit and ILS-Limit to limit dI / dt 2 2.5 3
VSUPLkg VSUP leakage current VSUP = 10 V for high side, controller disabled, TJ = 100°C 1 2 µA
ƒSWLBuck2/3 Buck switching frequency fOSC/5
VSense2/3 Feedback voltage With respect to 800-mV internal reference –1% 1%
DCBUCK2/3 Duty cycle High-side minimum on time 50 ns
Maximum duty cycle 99.8%
tDEAD_BUCK2/3 Shoot-through delay 20 ns
COMP2/3HTH COMP2/3 input threshold low 0.9 1.5 V
COMP2/3LTH COMP2/3 input threshold high VREG – 1.2 VREG – 0.3 V
RTIEOFF COMP23 COMP2/3 internal tie-off BUCK2/3 enabled. Resistor to VREG and GND, each 70 100 130 kΩ
VDIO2 3 Bootstrap-diode forward voltage IBOOT1 = –200 mA, VREG-BOOT2, VREG-BOOT3 1.1 1.2 V
BOOST CONVERTER
VBoost Boost adjustable-output voltage range Using 3.3-V input voltage, Ieak_switch ≤ 1 A 4.5 15 V
VBoost Boost adjustable-output voltage range Using 3.3-V input voltage Iloadmax = 20 mA, Ipeak_switch = 0.3 A 15 18.5 V
RDS-ON_BOOST Internal switch on-resistance VREG = 5.8 V 0.3 0.5 Ω
VSense5 Feedback voltage With respect to 800-mV internal reference –1% 1%
fSWLBOOST Boost switching frequency fOSC / 5 MHz
DCBOOST Maximum internal-MOSFET duty cycle at fSWLBOOST 90%
ICLBOOST Internal switch current limit 1 1.5 A
LINEAR REGULATOR LDO
VSUP4 Device operating range for LDO Recommended operating range 3 7 V
VLDO Regulated output range IOUT = 1 mA to 350 mA 0.8 5.25 V
VRefLDO DC output voltage tolerance at VSENSE4 VSENSE4 = 0.8 V (regulated at internal reference),
VSUP4 = 3 V to 7 V, IOUT = 1 mA to 350 mA		 –2% 2%
Vstep1 Load step 1 VSENSE4 = 0.8 V (regulated at internal reference),
IOUT = 1 mA to 101 mA, CLDO = 6 to 50 µF, trise = 1 µs		 –2% 2%
VSense4 Feedback voltage With respect to 800-mV internal reference –1% 1%
VDropout Dropout voltage IOUT = 350 mA, TJ = 25°C 127 143 mV
IOUT = 350 mA, TJ = 125°C 156 180
IOUT = 350 mA, TJ = 150°C 275 335
IOUT Output current VOUT in regulation –350 –1 mA
ILDO-CL Output current limit VOUT = 0 V, VSUP4 = 3 V to 7 V –1000 –400 mA
PSRRLDO Power-supply ripple rejection Vripple = 0.5 VPP, IOUT = 300 mA,
CLDO = 10 µF		 Frequency = 100 Hz 60 dB
Frequency = 4 kHz 50
Frequency = 150 kHz 25
LDOns10-100 Output noise 10 Hz – 100 Hz 10-µF output capacitance, VLDO = 2.5 V 20 µV/√(Hz)
LDOns100-1k Output noise 100 Hz – 10 kHz 10-µF output capacitance, VLDO = 2.5 V 6 µV/√(Hz)
CLDO Output capacitor Ceramic capacitor with ESR range, CLDO_ESR = 0 to 100 mΩ 6 50 µF
LED AND HIGH-SIDE SWITCH CONTROL
VHSSENSE Current-sense voltage VINPROT – HSSENSE, high-side switch in current limit 370 400 430 mV
VCMHSSENSE Common-mode range for current sensing See VINPROT 4 60 V
VHSOL_TH VINPROT – HSSENSE open load threshold Ramping negative 5 20 35 mV
Ramping positive 26 38 50
VHSOL_HY Open load hysteresis 10 18 28 mV
tHSOL_BLK Open-load blanking time 70 100 140 µs
VHS SC VINPROT – HSSENSE load short detection threshold Ramping positive 88 92.5 96 % VHSSENSE
Ramping negative from load short condition 87 90 93
VHSSC_HY VINPROT – HSSENSE short circuit hysteresis 1 % VHSSENSE
tHSS CL Net time in current-limit to disable driver 4 5 6 ms
tS HS Current-limit sampling interval 100 µs
VHSCTRLOFF Voltage at HSCTRL when OFF VINPROT
–0.5		 VINPROT V
VGS Clamp voltage between HSSENSE – HSCTRL 6.1 7.7 8.5 V
tON Turn on time Time from rising HSPWM until high-side switch in current limitation, ±5% settling 30 µs
Time from rising HSPWM until high-side switch until voltage-clamp between HSSENSE – HSCTRL active (within VGS limits) 30 60 µs
VOS_HS Overshoot during turnon VOS_HS = VINPROT - HSSENSE 400 mV
ICL_HSCTRL HSCTRL current limit 2 4.1 5 mA
RPU_HSCTRL Internal pullup resistors between VINPROT and HSCTRL 70 100 130 kΩ
RPU_HSCTRL-HSSENSE Internal pullup resistors between HSCTRL and HSSENSE 70 100 130 kΩ
VI_high High level input voltage HSPWM, VIO = 3.3 V 2 V
VI_low Low level input voltage HSPWM, VIO = 3.3 V 0.8 V
VI_hys Input voltage hysteresis HSPWM, VIO = 3.3 V 150 500 mV
fHS_IN HSPWM input frequency Design info, no device parameter 100 500 Hz
RSENSE External sense resistor Design info, no device parameter 1.5 50 Ω
CGS External MOSFET gate source capacitance 100 2000 pF
CGD External MOSFET gate drain capacitance 500 pF
REFERENCE VOLTAGE
VREF Reference voltage 3.3 V
VREF-tol Reference voltage tolerance IVREF = 5 mA –1% 1%
IREFCL Reference voltage current limit 10 25 mA
CVREF Capacitive load 0.6 5 µF
REFns10-100 Output noise 10 Hz–100 Hz 2.2-µF output capacitance, IVREF = 5 mA 20 µV/√(Hz)
REFns100-1k Output noise 100 Hz–10 kHz 2.2-µF output capacitance, IVREF = 5 mA 6 µV/√(Hz)
VREF_OK Reference voltage OK threshold Threshold, VREF falling 2.91 3.07 3.12 V
Hysteresis 14 70 140 mV
TREF_OK Reference voltage OK deglitch time 10 20 µs
SHUTDOWN COMPARATOR (TJ = –55°C TO +150°C)
VT_REF Shutdown comparator reference voltage IVT_REF = 20 µA. Measured as drop voltage with respect to VDVDD 1 17 500 mV
IVT_REF = 600 µA. Measured as drop voltage with respect to VDVDD. No VT_REF short-circuit detection. 200 420 1100
IVT_REFCL Shutdown comparator reference current limit VT_REF = 0 0.6 1 1.4 mA
VVT_REF SH VT_REF short circuit detection Threshold, VT_REF falling. Measured as drop voltage with respect to VDVDD 0.9 1.2 1.8 V
Hysteresis 130 mV
VTTH-H Input voltage threshold on VT, rising edge triggers shutdown This feature is specified by design to work down to –55°C. 0.48 0.50 0.52 VT_REF
VTTH-L Input voltage threshold on VT, falling voltage enables device operation This feature is specified by design to work down to –55°C. 0.46 0.48 0.52 VT_REF
VTTOL Threshold variation VTTH-H – VT_REF / 2, VTTH-L – VT_REF / 2 –20 20 mV
IVT_leak Leakage current TJ = –20°C to +150°C –400 –50 nA
TJ = –55°C to –20°C –200 –50
VT_REFOV VT_REF overvoltage threshold Threshold, VT_REF rising. Measured as drop voltage with respect to VDVDD 0.42 0.9 1.2 V
Hysteresis 100 mV
TVT_REF_FLT VT_REF fault deglitch time Overvoltage or short condition on VT_REF 10 20 µs
WAKE INPUT
VWAKE_ON Voltage threshold to enable device WAKE pin is a level sensitive input 3.3 3.7 V
tWAKE Min. pulse width at WAKE to enable device VWAKE = 4 V to suppress short spikes at WAKE pin 10 20 µs
VBAT UNDERVOLTAGE WARNING
VSSENSETH_L VSSENSE falling-threshold low SPI selectable, default after reset 4.3 4.7 V
VSSENSETH_H VSSENSE falling-threshold high SPI selectable 6.2 6.8 V
VSSENSE-HY VSSENSE hysteresis 0.2 V
tVSSENSE_BLK Blanking time VVSENSE < VSSENSETH_xx → IRQ asserted 10 35 µs
IVSLEAK Leakage current at VSSENSE LPM0 mode, VSSENSE 55 V 1 µA
IVSLEAK60 LPM0 mode, VSSENSE 60 V 100 µA
IVSLEAK80 LPM0 mode, VSSENSE 80 V 5 25 mA
RVSSENSE Internal resistance from VSSENSE to GND VSSENSE = 14 V, disabled in LPM0 mode 0.7 1 1.3 MΩ
VIN OVERVOLTAGE PROTECTION
VOVTH_H VIN overvoltage-shutdown threshold 1 (rising edge) Selectable with SPI 50 60 V
VOVTH_L VIN overvoltage-shutdown threshold 2 (rising edge) Selectable with SPI, default after reset 36 38 V
VOVHY VIN overvoltage hysteresis Threshold 1 0.2 1.7 3 V
Threshold 2; default after reset 1.5 2 2.5
tOFF BLK-H Overvoltage delay time VIN > VOVTH_H → GPFET off 1 µs
tOFF BLK-L Overvoltage blanking time VIN > VOVTH_L → GPFET off 10 20 µs
WINDOW WATCHDOG
ttimeout Timeout TESTSTART, TESTSTOP, VTCHECK , and RAMP mode:
Begins after entering each mode.
ACTIVE mode:
WD timeout begins with rising edge of RESN		 230 300 370 ms
tWD Watchdog window time Spread spectrum disabled 18 20 22 ms
Spread spectrum enable 19.8 22 24.2
tWD_FAIL Closed window time tWD / 4
tWD_BLK WD filter time 0.5 µs
VI_high High level input voltage WD, VIO = 3.3 V 2 V
VI_low Low level input voltage WD, VIO = 3.3 V 0.8 V
VI_hys Input voltage hysteresis WD, VIO = 3.3 V 150 500 mV
RESET AND IRQ BLOCK
tRESNHOLD RESN hold time 1.8 2 2.2 ms
VRESL Low level output voltage at RESN, PRESN and IRQ VIN ≥ 3 V, IxRESN = 2.5 mA 0 0.4 V
VRESL Low level output voltage at RESN and PRESN VIN = 0 V, VIO = 1.2 V, IxRESN = 1 mA 0 0.4 V
IRESLeak Leakage current at RESN, PRESN and IRQ Vtest = 5.5 V 1 µA
NRES Number of consecutive reset events for transfer to LPM0 7
tIRQHOLD IRQ hold time After VVSENSE < VSSENSETH for tVSSENSE_BLK 10 20 µs
tDR IRQ PRESN Rising edge delay of IRQ to rising edge of PRESN 2 µs
tDF RESN_PRESN Falling edge delay of RESN to PRESN / IRQ 2 µs
EXTERNAL PROTECTION
VCLAMP Gate to source clamp voltage VIN – GPFET, 100 µA 14 20 V
IGPFET Gate turn on current VIN = 14 V, GPFET = 2 V 15 25 µA
RDSONGFET Gate driver strength VIN = 14 V, turn off 25 Ω
THERMAL SHUTDOWN AND OVERTEMPERATURE PROTECTION
TSDTH Thermal shutdown Junction temperature 160 175 °C
TSDHY Hysteresis 20 °C
tSD-BLK Blanking time before thermal shutdown 10 20 µs
TOTTH Overtemperature flag Overtemperature flag is implemented as local temp sensors and expected to trigger before the thermal shutdown 150 165 °C
TOTHY Hysteresis 20 °C
tOT_BLK Blanking time before thermal over temperature 10 20 µs
VOLTAGE MONITORS BUCK1/2/3, VIO, LDO, BOOSTER
VMONTH_L Voltage monitor reference, falling edge REF = 0.8 V 90 92 94 %
VMONTH_H Voltage monitor reference, rising edge REF = 0.8 V 106 108 110 %
VMON_HY Voltage monitor hysteresis 2 %
VVIOMON_TH Undervoltage monitoring at VIO – falling edge 3 3.13 V
VVIOMON_HY UV_VIO hysteresis 0.05 V
tVMON_BLK Blanking time between UV or OV condition to RESN low UV/OV = BUCK1/2/3 UV = VIO 10 20 µs
tVMONTHL_BLK Blanking time between undervoltage condition to ERROR mode transition or corresponding SPI bit BUCK1/2/3 → ERROR mode LDO or BOOST → SPI bit set or turn off 1 ms
tVMONTHL_BLK1 Blanking time between undervoltage condition to ERROR mode transition VIO only 10 20 µs
tVMONTHH_BLK1 Blanking time between overvoltage condition to ERROR mode transition BUCK1/2/3 → ERROR mode VIO has no OV protection 10 20 µs
tVMONTHH_BLK2 Blanking time LDO and BOOST overvoltage condition to corresponding SPI bit or ERROR mode LDO or BOOST (ACTIVE mode) → SPI bit set or turn off LDO (VTCHECK or RAMP mode) → ERROR mode 20 40 µs
GND LOSS
VGLTH-low GND loss threshold low GND to PGNDx –0.31 –0.25 –0.19 V
VGLTH-high GND loss threshold high GND to PGNDx 0.19 0.25 0.31 V
tGL-BLK Blanking time between GND loss condition and transition to ERROR state 5 20 µs
POWER-UP SEQUENCING
tSTART1 Soft start time of BOOST From start until exceeding VMONTH_L + VMON_HY Level 0.7 2.7 ms
tSTART2 Soft start time of BUCK1/2/3 and LDO From start until exceeding VMONTH_L + VMON_HY Level 0.5 2 ms
tSTART Startup DVDD regulator From start until exceeding VMONTH_L + VMON_HY Level 3 ms
tSEQ2 Sequencing time from start of BUCK1 to BUCK2 and BOOST Internal SSDONE_BUCK1 signal 3 ms
tWAKE-RES Startup time from entering TESTSTART to RESN high GPFET = IRFR6215 14 ms
tSEQ1 Sequencing time from start of BOOST to BUCK3 Internal SSDONE_BOOST signal 1 4 ms
INTERNAL VOLTAGE REGULATORS (TJ = –55°C to +150°C)
VREG Internal regulated supply IVREG = 0 mA to 50 mA, VINPROT = 6.3 V to 40 V and
EXTSUP = 6.3 V to 12 V		 5.5 5.8 6.1 V
VEXTSUP-TH Switch over voltage IVREG = 0 mA to 50 mA and EXTSUP ramping positive,
ACTIVE mode		 4.4 4.6 4.8 V
VEXTSUP-HY Switch over hysteresis 100 200 300 mV
VREGDROP Dropout voltage on VREG IVREG = 50 mA, EXTSUP = 5 V / VINPROT = 5 V and
EXTSUP = 0 V / VINPROT = 4 V 		200 mV
IREG_CL Current limit on VREG EXTSUP = 0 V, VREG = 0 V –250 –50 mA
IREG_EXTSUP_CL EXTSUP ≥ 4.8 V, VREG = 0 V –250 –50 mA
CVREG Capacitive load 1.2 2.2 3.3 µF
VREG-OK VREG undervoltage threshold VREG rising 3.8 4 4.2 V
Hysteresis 350 420 490 mV
VDVDD Internal regulated low voltage supply 3.15 3.3 3.45 V
VDVDD UV DVDD undervoltage threshold DVDD falling 2.1 V
VDVDD OV DVDD overvoltage threshold DVDD rising 3.8 V
tDVDD OV Blanking time from DVDD overvoltage condition to shutdown mode transition 10 20 µs
GLOBAL PARAMETERS
RPU Internal pullup resistor at CSN pin 70 100 130 kΩ
RPD Internal pulldown resistor at pins: HSPWM , SDI, SCK, WD, S2(3) 70 100 130 kΩ
RPD-WAKE Internal pulldown resistor at WAKE pin 140 200 260 kΩ
ILKG Input pullup current at the VSENSE1–5 and VMON1–3 pins VTEST = 0.8 V –200 –100 –50 nA
fOSC Internal oscillator used for buck or boost switching frequency 4.6 4.9 5.2 MHz
fspread Spread-spectrum frequency range 0.8 × fOSC fOSC MHz
SPI
VI_high High-level input voltage CSN, SCK, SDI; VIO = 3.3 V 2 V
VI_low Low-level input voltage CSN, SCK, SDI; VIO = 3.3 V 0.8 V
VI_hys Input voltage hysteresis CSN, SCK, SDI; VIO = 3.3 V 150 500 mV
VO_high SDO-output high voltage VIO = 3.3 V ISDO = 1 mA 3 V
VO_low SDO-output low voltage VIO = 3.3 V ISDO = 1 mA 0.2 V
CSDO SDO capacitance 50 pF
(1) The quiescent current specification does not include the current flow through the external feedback resistor divider. Quiescent current is non-switching current, measured with no load on the output with VBAT = 13 V.
(2) Total current consumption measured on the EVM includes switching losses.
(3) RAMP and ACTIVE only.