The system MCU can activate the ABIST when the device is in the DIAGNOSTIC, ACTIVE, or SAFE state through the ABIST_GROUPx_START control bits in the SAFETY_ABIST_CTRL register when the ABIST_SCHED_EN configuration bit in the SAFETY_CFG2 register is not set.

In SAFE and DIAGNOSTIC states, ABIST runs immediately after setting ABIST_GROUPx_START bit in SAFETY_ABIST_CTRL register. In ACTIVE state, if ABIST_SCHED_EN ="0", ABIST runs only once after the ABIST_SCHED_DLY has expired. In ACTIVE state, if ABIST_SCHED_EN ="1", ABIST runs indefinitely with cycle time determined by ABIST_SCHED_DLY and it is stopped when ABIST_GROUPx_START bit is cleared.

The number of ABIST groups of tests depends on how many ABIST_GROUPx_START bits have been set while the ABIST_SCHED_EN configuration bit in the SAFETY_CFG2 register is not set. The options are four ABIST group of tests (or a full ABIST run), three ABIST group of tests, two ABIST group of tests, or just one ABIST group of tests. Examples of the different groups of tests include any of the following:

• ABIST Group 1 → ABIST Group 2 → ABIST Group 3 → ABIST Group 4, or
• ABIST Group 1 → ABIST Group 2 → ABIST Group 3, or
• ABIST Group 1 → ABIST Group 3 → ABIST Group 4, or
• ABIST Group 2 → ABIST Group 3 → ABIST Group 4, or
• ABIST Group 1 → ABIST Group 2, or
• ABIST Group 1 → ABIST Group 3, or
• ABIST Group 1 → ABIST Group 4, or
• ABIST Group 2 → ABIST Group 3, or
• ABIST Group 2 → ABIST Group 4, or
• ABIST Group 3 → ABIST Group 4, or
• ABIST Group 1, or
• ABIST Group 2, or
• ABIST Group 3, or
• ABIST Group 4

The full ABIST run, when the device is in the DIAGNOSTIC or ACTIVE state, includes a diagnostic check of the error monitor for the ENDRV/nIRQ output driver by allowing comparators in the overtemperature monitors (ABIST Group 4) to toggle the ENDRV/nIRQ pin in a known pattern for the duration of an analog comparator test, if any of the BUCKx/BOOST_OT_WARN_IRQ_EN bits are set. The ABIST of the overtemperature monitors includes both the warning and shutdown comparators. When the device is in the SAFE state, the ENDRV/nIRQ pin is always pulled to logic 0.

The diagnostics of the error monitor for the NRES output driver is performed by the LBIST.

At any time when an ABIST group of tests is set to run, the ABIST tests are activated only during the analog comparator output steady state (sampled analog comparator output matches respective deglitched output and SPI status bit).

If none of these conditions are met, then initiation of an ABIST run is delayed. The maximum wait time of an ABIST start is limited by its ABIST time-out function, which is ≈112 µs.

The full ABIST run is activated by setting all four ABIST_GROUPx_START control bits in the SAFETY_ABIST_CTRL register. As each ABIST group of tests are complete, a corresponding ABIST_GROUPx_DONE status bit is set in the SAFETY_ABIST_ERR_STAT1 status register. This ABIST_GROUPx_DONE status bit is cleared when the corresponding ABIST group of tests are running and is set to 1b when the corresponding ABIST group of tests are complete.

If any of scheduled diagnostic tests fail during an ABIST run or an ABIST time-out occurs and the ABIST_ACTIVE_FAIL_RESP bit is set to 0b, then the following occurs:

• The device goes into the SAFE state.
• One or more ABIST error status bits in the SAFETY_ABIST_ERR_STAT1 through
  the SAFETY_ABIST_ERR_STAT6 registers are set.
• The ENDRV/nIRQ pin is asserted low to interrupt the external system MCU.

This enables an interrupting of the external MCU in case of a detected ABIST failure and confirms its root cause by reading the SAFETY_ABIST_ERR_STAT1 through the SAFETY_ABIST_ERR_STAT6 status registers.

If any of the scheduled diagnostic tests fail during an ABIST run or an ABIST time-out occurs, and the ABIST_ACTIVE_FAIL_RESP bit is set to 1b, then the following occurs:

• The device does not change state.
• One or more ABIST error status bits in the SAFETY_ABIST_ERR_STAT1 through
  the SAFETY_ABIST_ERR_STAT6 registers are set.

Undervoltage and overvoltage comparator diagnostic tests do not impact the regulated output-voltage rails. This ABIST run does not include a circuit check of the regulator current-limit, VREG UV and VREG OV, and VIN UV and VIN OV diagnostic checks. When the VREG regulator is enabled, running the VREG UV and VREG OV diagnostics causes the VREG output to become uncontrollable, and for that reason it is excluded from this ABIST run.

Figure 11-8 ABIST Delayed Test Pulses

In the DIAGNOSTIC and SAFE state, the time interval, t₂ (time delay measured from the falling edge of test pulse n and the next rising edge of test pulse n+1), is a couple of system clock cycles.

1. ENDRV toggling is checked by the system MCU.

Figure 11-9 Full ABIST When the Device is in the DIAGNOSTIC, ACTIVE, or SAFE State

Figure 11-10 shows an example for running only the tests for the ABIST Group 1 and ABIST Group 4 groups by setting the ABIST_GROUP1_START and ABIST_GROUP42_START control bits in the
SAFETY_ABIST_CTRL register.

1. ENDRV toggling is checked by the system MCU.

Figure 11-10 Partial ABIST Run When the Device is in the DIAGNOSTIC, ACTIVE, or SAFE State