JAJSIR5C October   2019  – October 2023 TPS65313-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 デバイスの機能ブロック図
  6. 5 Revision History
  7. 6 概要 (続き)
  8. 7 Device Option Table
  9. 8 Pin Configuration and Functions
  10. 9 Specifications
    1. 9.1  Absolute Maximum Ratings
    2. 9.2  ESD Ratings
    3. 9.3  Recommended Operating Conditions
    4. 9.4  Thermal Information
    5. 9.5  Power-On-Reset, Current Consumption, and State Timeout Characteristics
    6. 9.6  PLL/Oscillator and SYNC_IN Pin Characteristics
    7. 9.7  Wide-VIN Synchronous Buck Regulator (Wide-VIN BUCK) Characteristics
    8. 9.8  Low-Voltage Synchronous Buck Regulator (LV BUCK) Characteristics
    9. 9.9  Synchronous Boost Converter (BOOST) Characteristics
    10. 9.10 Internal Voltage Regulator (VREG) Characteristics
    11. 9.11 Voltage Monitors for Regulators Characteristics
    12. 9.12 External General Purpose Voltage Monitor Characteristics
    13. 9.13 VIN and VIN_SAFE Under-Voltage and Over-Voltage Warning Characteristics
    14. 9.14 WAKE Input Characteristics
    15. 9.15 NRES (nRESET) Output Characteristics
    16. 9.16 ENDRV/nIRQ Output Characteristics
    17. 9.17 Analog DIAG_OUT
    18. 9.18 Digital INPUT/OUTPUT IOs (SPI Interface IOs, DIAG_OUT/SYNC_OUT, MCU_ERROR)
    19. 9.19 BUCK1, BUCK2, BOOST Thermal Shutdown / Over Temperature Protection Characteristics
    20. 9.20 PGNDx Loss Detection Characteristics
    21. 9.21 SPI Timing Requirements
    22. 9.22 SPI Characteristics
    23. 9.23 Typical Characteristics
  11. 10Parameter Measurement Information
  12. 11Detailed Description
    1. 11.1  Overview
    2. 11.2  Functional Block Diagram
    3. 11.3  Wide-VIN Buck Regulator (BUCK1)
      1. 11.3.1 Fixed-Frequency Voltage-Mode Step-Down Regulator
      2. 11.3.2 Operation
      3. 11.3.3 Voltage Monitoring (Monitoring and Protection)
      4. 11.3.4 Overcurrent Protection (Monitoring and Protection)
      5. 11.3.5 Thermal Warning and Shutdown Protection (Monitoring and Protection)
      6. 11.3.6 Overvoltage Protection (OVP) (Monitoring and Protection)
      7. 11.3.7 Extreme Overvoltage Protection (EOVP) (Monitoring and Protection)
    4. 11.4  Low-Voltage Buck Regulator (BUCK2)
      1. 11.4.1 Fixed-Frequency Peak-Current Mode Step-Down Regulator
      2. 11.4.2 Operation
      3. 11.4.3 Output Voltage Monitoring (Monitoring and Protection)
      4. 11.4.4 Overcurrent Protection (Monitoring and Protection)
      5. 11.4.5 Thermal Sensor Warning and Thermal Shutdown Protection (Monitoring and Protection)
      6. 11.4.6 Overvoltage Protection (OVP) (Monitoring and Protection)
    5. 11.5  Low-Voltage Boost Converter (BOOST)
      1. 11.5.1 Output Voltage Monitoring (Monitoring and Protection)
      2. 11.5.2 Overcurrent Protection (Monitoring and Protection)
      3. 11.5.3 Thermal Sensor Warning and Shutdown Protection (Monitoring and Protection)
      4. 11.5.4 Overvoltage Protection (OVP) (Monitoring and Protection)
    6. 11.6  VREG Regulator
    7. 11.7  BUCK1, BUCK2, and BOOST Switching Clocks and Synchronization (SYNC_IN) Clock
      1. 11.7.1 Internal fSW Clock Configuration (fSW Derived from an Internal Oscillator)
      2. 11.7.2 BUCK1 Switching Clock-Monitor Error (Internal fSW Clock Configuration)
      3. 11.7.3 BUCK2 Switching Clock-Monitor Error (Internal fSW Clock Configuration)
      4. 11.7.4 BOOST Switching Clock-Monitor Error (Internal fSW Clock Configuration)
      5. 11.7.5 External fSW Clock Configuration (fSW Derived from SYNC_IN and PLL Clocks)
        1. 11.7.5.1 SYNC_IN, PLL, and VCO Clock Monitors
        2. 11.7.5.2 BUCK1 Switching Clock-Monitor Error (External fSW Clock Configuration)
        3. 11.7.5.3 BUCK2 Switching Clock-Monitor Error (External fSW Clock Configuration)
        4. 11.7.5.4 BOOST Switching Clock-Monitor Error (External fSW Clock Configuration)
    8. 11.8  BUCK1, BUCK2, and BOOST Switching-Clock Spread-Spectrum Modulation
    9. 11.9  Monitoring, Protection and Diagnostics Overview
      1. 11.9.1  Safety Functions and Diagnostic Overview
      2. 11.9.2  Supply Voltage Monitor (VMON)
      3. 11.9.3  Clock Monitors
      4. 11.9.4  Analog Built-In Self-Test
        1. 11.9.4.1 ABIST During Power-Up or Start-Up Event
        2. 11.9.4.2 ABIST in the RESET state
        3. 11.9.4.3 ABIST in the DIAGNOSTIC, ACTIVE, and SAFE State
        4. 11.9.4.4 ABIST Scheduler in the ACTIVE State
      5. 11.9.5  Logic Built-In Self-Test
      6. 11.9.6  Junction Temperature Monitors
      7. 11.9.7  Current Limit
      8. 11.9.8  Loss of Ground (GND)
      9. 11.9.9  Diagnostic Output Pin (DIAG_OUT)
        1. 11.9.9.1 Analog MUX Mode on DIAG_OUT
        2. 11.9.9.2 Digital MUX Mode on DIAG_OUT
          1. 11.9.9.2.1 MUX-Output Control Mode
          2. 11.9.9.2.2 Device Interconnect Mode
      10. 11.9.10 Watchdog
        1. 11.9.10.1 WD Question and Answer Configurations
        2. 11.9.10.2 WD Failure Counter and WD Status
        3. 11.9.10.3 WD SPI Event Definitions
        4. 11.9.10.4 WD Q&A Sequence Run
        5. 11.9.10.5 WD Question and Answer Value Generation
          1. 11.9.10.5.1 WD Initialization Events
      11. 11.9.11 MCU Error Signal Monitor
      12. 11.9.12 NRES Driver
      13. 11.9.13 ENDRV/nIRQ Driver
      14. 11.9.14 CRC Protection for the Device Configuration Registers
      15. 11.9.15 CRC Protection for the Device EEPROM Registers
    10. 11.10 General-Purpose External Supply Voltage Monitors
    11. 11.11 Analog Wake-up and Failure Latch
    12. 11.12 Power-Up and Power-Down Sequences
    13. 11.13 Device Fail-Safe State Controller (Monitoring and Protection)
      1. 11.13.1 OFF State
      2. 11.13.2 INIT State
      3. 11.13.3 RESET State (ON Transition From the INIT State)
      4. 11.13.4 RESET State (ON Transition From DIAGNOSTIC, ACTIVE, and SAFE State)
      5. 11.13.5 DIAGNOSTIC State
      6. 11.13.6 ACTIVE State
      7. 11.13.7 SAFE State
      8. 11.13.8 State Transition Priorities
    14. 11.14 Wakeup
    15. 11.15 Serial Peripheral Interface (SPI)
      1. 11.15.1 SPI Command Transfer Phase
      2. 11.15.2 SPI Data Transfer Phase
      3. 11.15.3 Device SPI Status Flag Response Byte
      4. 11.15.4 Device SPI Data Response
      5. 11.15.5 Device SPI Master CRC (MCRC) Input
      6. 11.15.6 Device SPI Slave CRC (SCRC) Output
      7. 11.15.7 SPI Frame Overview
    16. 11.16 Register Maps
      1. 11.16.1 Device SPI Mapped Registers
        1. 11.16.1.1 Memory Maps
          1. 11.16.1.1.1 SPI Registers
  13. 12Applications, Implementation, and Layout
    1. 12.1 Application Information
    2. 12.2 Typical Application
      1. 12.2.1 Design Requirements
      2. 12.2.2 Detailed Design Procedure
        1. 12.2.2.1  Selecting the BUCK1, BUCK2, and BOOST Output Voltages
        2. 12.2.2.2  Selecting the BUCK1, BUCK2, and BOOST Inductors
        3. 12.2.2.3  Selecting the BUCK1 and BUCK2 Output Capacitors
        4. 12.2.2.4  Selecting the BOOST Output Capacitors
        5. 12.2.2.5  Input Filter Capacitor Selection for BUCK1, BUCK2, and BOOST
        6. 12.2.2.6  Input Filter Capacitors on AVIN and VIN_SAFE Pins
        7. 12.2.2.7  Bootstrap Capacitor Selection
        8. 12.2.2.8  Internal Linear Regulator (VREG) Output Capacitor Selection
        9. 12.2.2.9  EXTSUP Pin
        10. 12.2.2.10 WAKE Input Pin
        11. 12.2.2.11 VIO Supply Pin
        12. 12.2.2.12 External General-Purpose Voltage Monitor Input Pins (EXT_VSENSE1 and EXT_VSENSE2)
        13. 12.2.2.13 SYNC_IN Pin
        14. 12.2.2.14 MCU_ERR Pin
        15. 12.2.2.15 NRES Pin
        16. 12.2.2.16 ENDRV/nIRQ Pin
        17. 12.2.2.17 DIAG_OUT Pin
        18. 12.2.2.18 SPI Pins (NCS,SCK, SDI, SDO)
        19. 12.2.2.19 PBKGx, AGND, DGND, and PGNDx Pins
        20. 12.2.2.20 Calculations for Power Dissipation and Junction Temperature
          1. 12.2.2.20.1 BUCK1 Output Current Calculation
          2. 12.2.2.20.2 Device Power Dissipation Estimation
          3. 12.2.2.20.3 Device Junction Temperature Estimation
            1. 12.2.2.20.3.1 Example for Device Junction Temperature Estimation
      3. 12.2.3 Application Curves
      4. 12.2.4 Layout
        1. 12.2.4.1 Layout Guidelines
        2. 12.2.4.2 Layout Example
        3. 12.2.4.3 Considerations for Board-Level Reliability (BLR)
    3. 12.3 Power Supply Coupling and Bulk Capacitors
  14. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 ドキュメントの更新通知を受け取る方法
    3. 13.3 サポート・リソース
    4. 13.4 Trademarks
    5. 13.5 静電気放電に関する注意事項
    6. 13.6 用語集
  15. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.8 Low-Voltage Synchronous Buck Regulator (LV BUCK) Characteristics

VIN/AVIN/VIN_SAFE = 4 V to 36 V, TA = -40°C to 125°C, TJ up to 150°C, unless otherwise noted.(1)
POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
4.0 fSW_BUCK2 LV BUCK switching frequency 2.0 2.2 2.4 MHz
4.1 VSUP2_NOM LV BUCK supply voltage 3.3 V
4.1 VSUP2_NOM LV BUCK supply voltage 3.6 V
4.1a VSUP2 LV BUCK supply voltage range, in percentage of VSUP2_NOM 94 106 %
4.2 VBUCK2 LV BUCK output voltage 1.2 V
4.2 VBUCK2 LV BUCK output voltage 1.25 V
4.2 VBUCK2 LV BUCK output voltage 1.8 V
4.2 VBUCK2 LV BUCK output voltage 2.3 V
4.3 VBUCK2_DC_ACCURACY LV BUCK DC output voltage accuracy IBUCK2_LOAD = 0 A to max(IBUCK2_LOAD), measured at VSENSE2 pin(3) -1.5 +1.5 %
4.4a IBUCK2_LOAD LV BUCK load current(2) VSUP2 = 3.3 V for VBUCK2 = 1.2 V, 1.25 V, 1.8 V
2 A
4.4b IBUCK2_LOAD LV BUCK load current(2) VSUP2 = 3.3 V , VBUCK2 = 2.3 V
 1.5 A
4.5a VBUCK2_RIPPLE LV BUCK output peak voltage ripple (0.5 × VPP), in percentage of target regulation voltage IBUCK2_LOAD = max(IBUCK2_LOAD)(3)

 0.6 %
4.5b VBUCK2_RIPPLE_SSM LV BUCK output peak voltage ripple (0.5 × VPP), in percentage of target regulation voltage, when fSW spread spectrum clock modulation is enabled IBUCK2_LOAD = max(IBUCK2_LOAD)(3)
 0.6 %
4.6 ISUP_BUCK2_NO_LOAD LV BUCK no-load supply current IBUCK2_LOAD = 0 A(3)
 3 6.5 mA
4.7 RDSON_HS_BUCK2 ON resistance of high-side switch FET VGS=4.5V, IDS = 1.0A 90 180 mΩ
4.8 RDSON_LS_BUCK2 ON resistance of low-side switch FET VGS=4.5V, IDS = 1.0A 110 220 mΩ
4.11 tSS_BUCK2 LV BUCK soft-start duration Measured from LV BUCK enable event to VBUCK2 crossing its UV threshold. 
COUT = 100μF
 0.85 ms
4.12 IHS_LIMIT_BUCK2 High-side switch current limit for weak-short/hard-short conditions 2.6 3.5 4.5 A
4.13 ILS_LIMIT_BUCK2 Low-side switch current limit for functional over-load conditions
 2.1 2.7 3.3 A
4.14 ILS_SINK_BUCK2 Low-side switch sinking current limit -1.1 -0.8 -0.5 A
4.18a RDISCH_BUCK2 LV BUCK internal discharge resistance when the device is in RESET state LV BUCK disabled, VBUCK2 = 1 V 100 200 400 Ω
4.18b RDISCH_BUCK2_OFF LV BUCK internal discharge resistance when the device is OFF state LV BUCK disabled, VBUCK2 = 1 V 400 800 1200 Ω
4.19 ∆VBUCK2_LINEREG_DC Output voltage line regulation

NOTE: DC line regulation as output voltage change in % ( ∆VBUCK2 / VBUCK2 ) as VSUP2 is changing from VSUP2_MIN to VSUP2_MAX		 0.97 × VSUP2_NOM ≤ VSUP2 ≤ 1.03 × VSUP2_NOM,
IBUCK2_LOAD = 1.5 A(3)		 0.1 0.2 %
4.20 ∆VBUCK2_LOADREG_DC Output voltage load regulation

NOTE: DC load regulation as output voltage change in % ( ∆VBUCK2 / VBUCK2 ) as IBUCK2 changes from 0A to 2A		 IBUCK2_LOAD = 0 A to max(IBUCK2_LOAD)(3)
 0.2 0.3 %
4.21 VBUCK2_LOAD_TRAN1 LV BUCK load transient regulation, in percentage of steady-state regulation voltage

 IBUCK2_LOAD load step:
- 0.5 A to 1.5 A
- 1.5 A down to 0.5 A
dIBUCK2_LOAD/dt = 300 mA/μs

 -6 6 %
4.22 tSETTLE_BUCK2 Load transient recovery time to 1% below starting point, or 1% above starting point. IBUCK2_LOAD load step:
- 0.5 A to 1.5 A
- 1.5 A down to 0.5 A
dIBUCK2_LOAD/dt = 300 mA/μs		 20 µs
4.24 VBUCK2_RESTART_LEVEL LV BUCK output voltage level before ramp-up starts, in percentage of target regulation voltage NOTE: when there is a shutdown event followed by new start-up event, device cannot start-up again until LV BUCK2 discharges below this level 45 %
(1) Total output capacitance, CBUCK2, including board parasitic capacitance, should not exceed 100 μF.
(2) Advanced thermal design may be required to avoid thermal shutdown.
(3) Refer to Regulator LC Selection table for inductor and capacitor values.