The device starts with downloading the EEPROM trim and configuration content to the EEPROM-mapped registers. The EEPROM mapped register content is protected by a CRC. The CRC is a safety mechanism to protect the device from failure during an EEPROM content download, corruption of EEPROM-mapped register content, or both. If an EEPROM register-content CRC error is detected, the device goes into the OFF state and latches the EE_CRC error in the Analog_Latch.

After the trim settings are downloaded from the EEPROM without error, the device checks for any overtemperature conditions by confirming that the die junction temperature is less than its warning threshold level (T_{WARN_TH} – T_{WARN_TH_HYS}). If the die junction temperature is greater than this level, the device stays in the RESET state. If the die junction temperature does not drop below its warning threshold level, before the timer for the RESET state time-out expires, then the device goes back to the OFF state and flag for the RESET state time-out is latched in the Analog_Latch.

The device also starts the power-up ABIST to check the monitoring and protection mechanisms for the VREG regulator and current-limit comparators of the switched-mode regulators. The ABIST diagnostic test runs before enabling switched-mode regulators to make sure system reset is not released before the regulated supplies exceed their UV-threshold levels. This is because a failure of the voltage monitoring circuit or the protection circuit cannot protect the regulators in case of device power-up with an external short present or internal regulator failure. If the ABIST diagnostic test passes, the switching voltage regulators can be enabled.

When all regulators exceed their undervoltage threshold levels, an NRES system extension starts. The NRES extension time is configurable through the NRES_EXT[1:0] bits in the DEV_CFG4 configuration register. The extension time is configurable from 2 ms to 32 ms with a 10-ms increment.

During an NRES extension time, the device runs the ABIST and then runs the logic BIST (LBIST). The ABIST in the RESET state is performed on all voltage, temperature, and clock monitors except the on the monitoring and protection circuits that are checked by the power-up ABIST. The power-up ABIST is performed when the device goes from the INIT state to the RESET state before the switched-mode regulators are enabled. Therefore, the minimum NRES extension time is longer than the total run time of both the ABIST and LBIST, which is less than 2 ms. If any BIST fails, the device goes into the SAFE state after the NRES extension time elapses. The system MCU selects how to continue in the SAFE state.

All monitoring and protection functions stay enabled in the RESET state except the watchdog function.