JAJSIR5C October   2019  – October 2023 TPS65313-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 デバイスの機能ブロック図
  6. 5 Revision History
  7. 6 概要 (続き)
  8. 7 Device Option Table
  9. 8 Pin Configuration and Functions
  10. 9 Specifications
    1. 9.1  Absolute Maximum Ratings
    2. 9.2  ESD Ratings
    3. 9.3  Recommended Operating Conditions
    4. 9.4  Thermal Information
    5. 9.5  Power-On-Reset, Current Consumption, and State Timeout Characteristics
    6. 9.6  PLL/Oscillator and SYNC_IN Pin Characteristics
    7. 9.7  Wide-VIN Synchronous Buck Regulator (Wide-VIN BUCK) Characteristics
    8. 9.8  Low-Voltage Synchronous Buck Regulator (LV BUCK) Characteristics
    9. 9.9  Synchronous Boost Converter (BOOST) Characteristics
    10. 9.10 Internal Voltage Regulator (VREG) Characteristics
    11. 9.11 Voltage Monitors for Regulators Characteristics
    12. 9.12 External General Purpose Voltage Monitor Characteristics
    13. 9.13 VIN and VIN_SAFE Under-Voltage and Over-Voltage Warning Characteristics
    14. 9.14 WAKE Input Characteristics
    15. 9.15 NRES (nRESET) Output Characteristics
    16. 9.16 ENDRV/nIRQ Output Characteristics
    17. 9.17 Analog DIAG_OUT
    18. 9.18 Digital INPUT/OUTPUT IOs (SPI Interface IOs, DIAG_OUT/SYNC_OUT, MCU_ERROR)
    19. 9.19 BUCK1, BUCK2, BOOST Thermal Shutdown / Over Temperature Protection Characteristics
    20. 9.20 PGNDx Loss Detection Characteristics
    21. 9.21 SPI Timing Requirements
    22. 9.22 SPI Characteristics
    23. 9.23 Typical Characteristics
  11. 10Parameter Measurement Information
  12. 11Detailed Description
    1. 11.1  Overview
    2. 11.2  Functional Block Diagram
    3. 11.3  Wide-VIN Buck Regulator (BUCK1)
      1. 11.3.1 Fixed-Frequency Voltage-Mode Step-Down Regulator
      2. 11.3.2 Operation
      3. 11.3.3 Voltage Monitoring (Monitoring and Protection)
      4. 11.3.4 Overcurrent Protection (Monitoring and Protection)
      5. 11.3.5 Thermal Warning and Shutdown Protection (Monitoring and Protection)
      6. 11.3.6 Overvoltage Protection (OVP) (Monitoring and Protection)
      7. 11.3.7 Extreme Overvoltage Protection (EOVP) (Monitoring and Protection)
    4. 11.4  Low-Voltage Buck Regulator (BUCK2)
      1. 11.4.1 Fixed-Frequency Peak-Current Mode Step-Down Regulator
      2. 11.4.2 Operation
      3. 11.4.3 Output Voltage Monitoring (Monitoring and Protection)
      4. 11.4.4 Overcurrent Protection (Monitoring and Protection)
      5. 11.4.5 Thermal Sensor Warning and Thermal Shutdown Protection (Monitoring and Protection)
      6. 11.4.6 Overvoltage Protection (OVP) (Monitoring and Protection)
    5. 11.5  Low-Voltage Boost Converter (BOOST)
      1. 11.5.1 Output Voltage Monitoring (Monitoring and Protection)
      2. 11.5.2 Overcurrent Protection (Monitoring and Protection)
      3. 11.5.3 Thermal Sensor Warning and Shutdown Protection (Monitoring and Protection)
      4. 11.5.4 Overvoltage Protection (OVP) (Monitoring and Protection)
    6. 11.6  VREG Regulator
    7. 11.7  BUCK1, BUCK2, and BOOST Switching Clocks and Synchronization (SYNC_IN) Clock
      1. 11.7.1 Internal fSW Clock Configuration (fSW Derived from an Internal Oscillator)
      2. 11.7.2 BUCK1 Switching Clock-Monitor Error (Internal fSW Clock Configuration)
      3. 11.7.3 BUCK2 Switching Clock-Monitor Error (Internal fSW Clock Configuration)
      4. 11.7.4 BOOST Switching Clock-Monitor Error (Internal fSW Clock Configuration)
      5. 11.7.5 External fSW Clock Configuration (fSW Derived from SYNC_IN and PLL Clocks)
        1. 11.7.5.1 SYNC_IN, PLL, and VCO Clock Monitors
        2. 11.7.5.2 BUCK1 Switching Clock-Monitor Error (External fSW Clock Configuration)
        3. 11.7.5.3 BUCK2 Switching Clock-Monitor Error (External fSW Clock Configuration)
        4. 11.7.5.4 BOOST Switching Clock-Monitor Error (External fSW Clock Configuration)
    8. 11.8  BUCK1, BUCK2, and BOOST Switching-Clock Spread-Spectrum Modulation
    9. 11.9  Monitoring, Protection and Diagnostics Overview
      1. 11.9.1  Safety Functions and Diagnostic Overview
      2. 11.9.2  Supply Voltage Monitor (VMON)
      3. 11.9.3  Clock Monitors
      4. 11.9.4  Analog Built-In Self-Test
        1. 11.9.4.1 ABIST During Power-Up or Start-Up Event
        2. 11.9.4.2 ABIST in the RESET state
        3. 11.9.4.3 ABIST in the DIAGNOSTIC, ACTIVE, and SAFE State
        4. 11.9.4.4 ABIST Scheduler in the ACTIVE State
      5. 11.9.5  Logic Built-In Self-Test
      6. 11.9.6  Junction Temperature Monitors
      7. 11.9.7  Current Limit
      8. 11.9.8  Loss of Ground (GND)
      9. 11.9.9  Diagnostic Output Pin (DIAG_OUT)
        1. 11.9.9.1 Analog MUX Mode on DIAG_OUT
        2. 11.9.9.2 Digital MUX Mode on DIAG_OUT
          1. 11.9.9.2.1 MUX-Output Control Mode
          2. 11.9.9.2.2 Device Interconnect Mode
      10. 11.9.10 Watchdog
        1. 11.9.10.1 WD Question and Answer Configurations
        2. 11.9.10.2 WD Failure Counter and WD Status
        3. 11.9.10.3 WD SPI Event Definitions
        4. 11.9.10.4 WD Q&A Sequence Run
        5. 11.9.10.5 WD Question and Answer Value Generation
          1. 11.9.10.5.1 WD Initialization Events
      11. 11.9.11 MCU Error Signal Monitor
      12. 11.9.12 NRES Driver
      13. 11.9.13 ENDRV/nIRQ Driver
      14. 11.9.14 CRC Protection for the Device Configuration Registers
      15. 11.9.15 CRC Protection for the Device EEPROM Registers
    10. 11.10 General-Purpose External Supply Voltage Monitors
    11. 11.11 Analog Wake-up and Failure Latch
    12. 11.12 Power-Up and Power-Down Sequences
    13. 11.13 Device Fail-Safe State Controller (Monitoring and Protection)
      1. 11.13.1 OFF State
      2. 11.13.2 INIT State
      3. 11.13.3 RESET State (ON Transition From the INIT State)
      4. 11.13.4 RESET State (ON Transition From DIAGNOSTIC, ACTIVE, and SAFE State)
      5. 11.13.5 DIAGNOSTIC State
      6. 11.13.6 ACTIVE State
      7. 11.13.7 SAFE State
      8. 11.13.8 State Transition Priorities
    14. 11.14 Wakeup
    15. 11.15 Serial Peripheral Interface (SPI)
      1. 11.15.1 SPI Command Transfer Phase
      2. 11.15.2 SPI Data Transfer Phase
      3. 11.15.3 Device SPI Status Flag Response Byte
      4. 11.15.4 Device SPI Data Response
      5. 11.15.5 Device SPI Master CRC (MCRC) Input
      6. 11.15.6 Device SPI Slave CRC (SCRC) Output
      7. 11.15.7 SPI Frame Overview
    16. 11.16 Register Maps
      1. 11.16.1 Device SPI Mapped Registers
        1. 11.16.1.1 Memory Maps
          1. 11.16.1.1.1 SPI Registers
  13. 12Applications, Implementation, and Layout
    1. 12.1 Application Information
    2. 12.2 Typical Application
      1. 12.2.1 Design Requirements
      2. 12.2.2 Detailed Design Procedure
        1. 12.2.2.1  Selecting the BUCK1, BUCK2, and BOOST Output Voltages
        2. 12.2.2.2  Selecting the BUCK1, BUCK2, and BOOST Inductors
        3. 12.2.2.3  Selecting the BUCK1 and BUCK2 Output Capacitors
        4. 12.2.2.4  Selecting the BOOST Output Capacitors
        5. 12.2.2.5  Input Filter Capacitor Selection for BUCK1, BUCK2, and BOOST
        6. 12.2.2.6  Input Filter Capacitors on AVIN and VIN_SAFE Pins
        7. 12.2.2.7  Bootstrap Capacitor Selection
        8. 12.2.2.8  Internal Linear Regulator (VREG) Output Capacitor Selection
        9. 12.2.2.9  EXTSUP Pin
        10. 12.2.2.10 WAKE Input Pin
        11. 12.2.2.11 VIO Supply Pin
        12. 12.2.2.12 External General-Purpose Voltage Monitor Input Pins (EXT_VSENSE1 and EXT_VSENSE2)
        13. 12.2.2.13 SYNC_IN Pin
        14. 12.2.2.14 MCU_ERR Pin
        15. 12.2.2.15 NRES Pin
        16. 12.2.2.16 ENDRV/nIRQ Pin
        17. 12.2.2.17 DIAG_OUT Pin
        18. 12.2.2.18 SPI Pins (NCS,SCK, SDI, SDO)
        19. 12.2.2.19 PBKGx, AGND, DGND, and PGNDx Pins
        20. 12.2.2.20 Calculations for Power Dissipation and Junction Temperature
          1. 12.2.2.20.1 BUCK1 Output Current Calculation
          2. 12.2.2.20.2 Device Power Dissipation Estimation
          3. 12.2.2.20.3 Device Junction Temperature Estimation
            1. 12.2.2.20.3.1 Example for Device Junction Temperature Estimation
      3. 12.2.3 Application Curves
      4. 12.2.4 Layout
        1. 12.2.4.1 Layout Guidelines
        2. 12.2.4.2 Layout Example
        3. 12.2.4.3 Considerations for Board-Level Reliability (BLR)
    3. 12.3 Power Supply Coupling and Bulk Capacitors
  14. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 ドキュメントの更新通知を受け取る方法
    3. 13.3 サポート・リソース
    4. 13.4 Trademarks
    5. 13.5 静電気放電に関する注意事項
    6. 13.6 用語集
  15. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

11.9.9.2 Digital MUX Mode on DIAG_OUT

Table 11-7 lists the selectable digital internal signals on the DIAG_OUT pin. In the DIAG_CTRL register, the MUX_CFG[1:0] bits must be set to 01b for DMUX mode. In this mode, the analog output buffer (see DIAG_OUT Analog and Digital MUX) is in the high-impedance state.

Most of these signals are internal error signals which influence the device state and behavior of the NRES and ENDRV pins.

Table 11-7 DMUX Channel Selection
CHANNEL
NUMBER		 SIGNAL NAME DESCRIPTION CHANNEL GROUP
DIAG_MUX_SEL[6:4]		 CHANNEL NUMBER
SELECTION THROUGH
DIAG_MUX_SEL[3:0]
D0.0 RESERVED Reserved, logic 0 000b 0000b
D0.1 VREG_UV VREG undervoltage comparator output 000b 0001b
D0.2 - D0.6 RESERVED Reserved, logic 0 000b 0010b through 0110b
D0.7 BUCK1_UV BUCK1 undervoltage comparator 000b 0111b
D0.8 BUCK1_OV BUCK1 overvoltage comparator 000b 1000b
D0.9 BUCK2_UV BUCK2 undervoltage comparator 000b 1001b
D0.10 BUCK2_OV BUCK2 overvoltage comparator 000b 1010b
D0.11 BOOST_UV BOOST undervoltage comparator 000b 1011b
D0.12 BOOST_OV BOOST overvoltage comparator 000b 1100b
D0.13 RESERVED Reserved, logic 0 000b 1101b
D0.14 RESERVED Reserved, logic 0 000b 1110b
D0.15 VIO_OV VIO overvoltage comparator 000b 1111b
D1.0 SYNC_OUT Synchronization SYNC_OUT clock output 001b 0000b
D1.1 SYSCLK System-clock source (8 MHz ± 5%) 001b 0001b
D1.2 PLL_CLK PLL clock output 001b 0010b
D1.3 SYNC_IN Synchronization SYNC_IN clock source 001b 0011b
D1.4 fSW_BUCK1_CLK BUCK1 switched-mode regulator clock source 001b 0100b
D1.5 fSW_BUCK2_CLK BUCK2 switched-mode regulator clock source 001b 0101b
D1.6 RESERVED Reserved, logic 0 001b 0110b
D1.7 fSW_BOOST_CLK BOOST switched-mode regulator clock source 001b 0111b
D1.8–D1.15 RESERVED Reserved, logic 0 001b 1000b through 1111b
D2.0 RESERVED Reserved, logic 0 010b 0000b
D2.1 BUCK1_HS_ILIM BUCK1 HS current-limit signal 010b 0001b
D2.2 BUCK1_LS_ILIM BUCK1 LS current-limit signal 010b 0010b
D2.3 BUCK1_LS_S_ILIM BUCK1 LS sink current-limit signal 010b 0011b
D2.4 BUCK1_OVP BUCK1 overvoltage protection comparator 010b 0100b
D2.5 BUCK1_OT BUCK1 overtemperature 010b 0101b
D2.6 BUCK2_HS_ILIM BUCK2 HS current-limit signal 010b 0110b
D2.7 BUCK2_LS_ILIM BUCK2 LS current-limit signal 010b 0111b
D2.8 BUCK2_LS_S_ILIM BUCK2 LS sink current-limit signal 010b 1000b
D2.9 BUCK2_OVP BUCK2 overvoltage protection comparator 010b 1001b
D2.10 BUCK2_OT BUCK2 overtemperature 010b 1010b
D2.11 BOOST_LS_ILIM BOOST LS current-limit signal 010b 1011b
D2.12 BOOST_HS_ILIM BOOST HS current-limit signal 010b 1100b
D2.13 BOOST_HS_S_ILIM BOOST HS sink current-limit signal 010b 1101b
D2.14 BOOST_OVP BOOST overvoltage protection comparator 010b 1110b
D2.15 BOOST_OT BOOST overtemperature 010b 1111b
D3.0 RESERVED Reserved, logic 0 011b 0000b
D3.1 BUCK1_OT_WARN BUCK1 overtemperature warning 011b 0001b
D3.2 BUCK2_OT_WARN BUCK2 overtemperature warning 011b 0010b
D3.3 BOOST_OT_WARN BOOST overtemperature warning 011b 0011b
D3.4 – D3.15 RESERVED Reserved, logic 0 011b 0100b through 1111b
D4.0 – D4.15 RESERVED Reserved, logic 0 100b 0000b through 1111b
D5.0 – D5.15 RESERVED Reserved, logic 0 101b 0000b through 1111b
D6.0 – D6.15 RESERVED Reserved, logic 0 110b 0000b through 1111b
D7.0 - D7.15 RESERVED Reserved, logic 0 111b 0000b through 1111b